Can anybody give a clear explanation of how variable assignment really works in Makefiles. 

What is the difference between :

     VARIABLE = value
     VARIABLE ?= value
     VARIABLE := value
     VARIABLE += value
     
I have read the [section][1] in GNU Make&#39;s manual, but it still doesn&#39;t make sense to me. 



  [1]: http://www.gnu.org/software/make/manual/make.html#Reading-Makefiles

What is the difference between the GNU Makefile variable assignments =, ?=, := and +=?

For example, I have something like this in my makefile:

    all:
         cd some_directory

But when I typed `make` I saw only &#39;cd some_directory&#39;, like in the `echo` command.


How do I write the &#39;cd&#39; command in a makefile?

I use CMake with GNU Make and would like to see all commands exactly (for example how the compiler is executed, all the flags etc.).

GNU make has `--debug`, but it does not seem to be that helpful are there any other options? Does CMake provide additional flags in the generated Makefile for debugging purpose?

Using CMake with GNU Make: How can I see the exact commands?

In my makefile, I have a variable &#39;NDK_PROJECT_PATH&#39;, my question is how can I print it out when it compiles?

I read https://stackoverflow.com/questions/3707517/make-file-echo-displaying-path-string and I tried:

    @echo $(NDK_PROJECT_PATH)
    @echo $(value NDK_PROJECT_PATH)

Both gives me 

    &quot;build-local.mk:102: *** missing separator.  Stop.&quot;

Any one knows why it is not working for me?




How to print out a variable in makefile

I&#39;ve used rake a bit (a Ruby make program), and it has an option to get a list of all the available targets, eg

    &gt; rake --tasks
    rake db:charset      # retrieve the charset for your data...
    rake db:collation    # retrieve the collation for your da...
    rake db:create       # Creates the databases defined in y...
    rake db:drop         # Drops the database for your curren...
    ...

but there seems to be no option to do this in GNU make. 

Apparently the code is almost there for it, as of 2007 - http://www.mail-archive.com/help-make@gnu.org/msg06434.html. 

Anyway, I made little hack to extract the targets from a makefile, which you can include in a makefile. 

    list:
        @grep &#39;^[^#[:space:]].*:&#39; Makefile

It will give you a list of the defined targets. It&#39;s just a start - it doesn&#39;t filter out the dependencies, for instance. 

    &gt; make list
    list:
    copy:
    run:
    plot:
    turnin:



How do you get the list of targets in a makefile?

I have a several Makefiles in app specific directories like this:

    /project1/apps/app_typeA/Makefile
    /project1/apps/app_typeB/Makefile
    /project1/apps/app_typeC/Makefile

Each Makefile includes a .inc file in this path one level up:

    /project1/apps/app_rules.inc

Inside app_rules.inc I&#39;m setting the destination of where I want the binaries to be placed when built. I want all binaries to be in their respective `app_type` path:

    /project1/bin/app_typeA/

**I tried using `$(CURDIR)`**, like this:

    OUTPUT_PATH = /project1/bin/$(CURDIR)

but instead I got the binaries buried in the entire path name like this: **(notice the redundancy)**

    /project1/bin/projects/users/bob/project1/apps/app_typeA

What can I do to get the &quot;current directory&quot; of execution so that I can know just the **`app_typeX`** in order to put the binaries in their respective types folder?

How to get current relative directory of your Makefile?

In my GNUmakefile, I would like to have a rule that uses a temporary directory.  For example:

    out.tar: TMP := $(shell mktemp -d)
            echo hi $(TMP)/hi.txt
            tar -C $(TMP) cf $@ .
            rm -rf $(TMP)

As written, the above rule creates the temporary directory at the time that the rule is *parsed*.  This means that, even I don&#39;t make out.tar all the time, many temporary directories get created.  I would like to avoid my /tmp being littered with unused temporary directories.

Is there a way to cause the variable to only be defined when the rule is fired, as opposed to whenever it is defined?

My main thought is to dump the mktemp and tar into a shell script but that seems somewhat unsightly.

Define make variable at rule execution time

I&#39;m following the instructions of someone whose repository I cloned to my machine. I want to use the `make` command as part of setting up the code environment, but I&#39;m using Windows. I searched online, but I could only find a `make.exe` file, a `make-4.1.tar.gz` file (I don&#39;t know what to do with it next) and instructions for how to download MinGW (for GNU; but after installing it I didn&#39;t find any mention of &quot;make&quot;).

How do I use `make` in Windows without a GNU compiler or related packages?

How to install and use &quot;make&quot; in Windows?

In the GNU Makefile manual, it [mentions][1] these prefixes.

&gt; If .ONESHELL is provided, then only the first line of the recipe will be checked for the special prefix characters (‘@’, ‘-’, and ‘+’).

What do these prefixes do, and where are they mentioned?

  [1]: http://www.gnu.org/software/make/manual/make.html#One-Shell

What do @, - and + do as prefixes to recipe lines in Make?

I have the following makefile for my project, and I&#39;d like to configure it for release and debug builds. In my code, I have lots of `#ifdef DEBUG` macros in place, so it&#39;s simply a matter of setting this macro and adding the `-g3 -gdwarf2` flags to the compilers. How can I do this?

    $(CC) = g++ -g3 -gdwarf2
    $(cc) = gcc -g3 -gdwarf2
    
    all: executable
    
    executable: CommandParser.tab.o CommandParser.yy.o Command.o
    	g++ -g -o output CommandParser.yy.o CommandParser.tab.o Command.o -lfl
    
    CommandParser.yy.o: CommandParser.l 
    	flex -o CommandParser.yy.c CommandParser.l
    	gcc -g -c CommandParser.yy.c
    
    CommandParser.tab.o: CommandParser.y
    	bison -d CommandParser.y
    	g++ -g -c CommandParser.tab.c
    
    Command.o: Command.cpp
    	g++ -g -c Command.cpp
    
    clean:
    	rm -f CommandParser.tab.* CommandParser.yy.* output *.o

Just to clarify, when I say release/debug builds, I want to be able to just type `make` and get a release build or `make debug` and get a debug build, without manually commenting out things in the makefile.


How can I configure my makefile for debug and release builds?

What does the following do in a Makefile?

    rule: $(deps)
        @:

I can&#39;t seem to find this in the make manual.

What does @: (at symbol colon) mean in a Makefile?

I&#39;m getting some unexpected results calling one makefile from another.  I have two makefiles, one called `/path/to/project/makefile` and one called `/path/to/project/gtest-1.4.0/make/Makefile`.  I&#39;m attempting to have the former call the latter.  In /path/to/project/makefile, I have

    dev: $(OBJ_FILES)
      $(CPPC) $(LIBS) $(FLAGS_DEV) $(OBJ_FILES) -o $(BIN_DIR)/$(PROJECT)
      $(MAKE) -f ./gtest-1.4.0/make/Makefile

    clean:
      rm -f ./*~ ./gmon.out ./core $(SRC_DIR)/*~ $(OBJ_DIR)/*.o
      rm -f ../svn-commit.tmp~
      rm -f $(BIN_DIR)/$(PROJECT)
      make -f gtest-1.4.0/make/Makefile clean

And in `/path/to/project/gtest-1.4.0/make/Makefile` I have

    all: $(TESTS)

    clean:
      rm -f $(TESTS) gtest.a gtest_main.a *.o

Issuing the following:

    cd /path/to/project
    make

Outputs:

    make -f ./gtest-1.4.0/make/Makefile
    make[1]: Entering directory `/path/to/project&#39;
    make[1]: Nothing to be done for `all&#39;.
    make[1]: Leaving directory `/path/to/project&#39;

However, when I issue these commands:

    cd /path/to/project
    make clean

I see:

    make -f gtest-1.4.0/make/Makefile clean
    make[1]: Entering directory `/path/to/project&#39;
    rm -f  gtest.a gtest_main.a *.o
    make[1]: Leaving directory `/path/to/project&#39;

I don&#39;t understand: In both cases, `/path/to/project/makefile` is telling me it&#39;s entering the current working directory.  In the first case, it doesn&#39;t think it has work to do (when it does) and in the second case, it&#39;s able to find the appropriate directive (when the output is telling me it&#39;s looking in the wrong directory) yet it tries to run the `rm` command in `/path/to/project`, instead of `/path/to/makefile/gtest-1.4.0/make/`.

Am I missing something fundamental to calling makefiles from one another?  Have I made an egregious conceptual mistake, or hit a common pitfall?  How do I effectively change directories and call a second makefile from within the first?  My understanding was that simply calling `make -f &lt;name&gt;` would be enough.

This is make/gmake 3.81 in bash.

How to call Makefile from another Makefile?

What&#39;s the difference between CPPFLAGS and CXXFLAGS in GNU Make?

Difference between CPPFLAGS and CXXFLAGS in GNU Make

I am trying to understand the difference between &#39;gmake&#39; and &#39;make&#39;?  

On my linux box they are identical:

    % gmake --version
    GNU Make 3.81
    Copyright (C) 2006  Free Software Foundation, Inc.
    This is free software; see the source for copying conditions.
    There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
    PARTICULAR PURPOSE.

    % make --version
    GNU Make 3.81
    Copyright (C) 2006  Free Software Foundation, Inc.
    This is free software; see the source for copying conditions.
    There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
    PARTICULAR PURPOSE.

I am guessing this isn&#39;t the same on all platforms?
Is there a good reason to use one over the other?  
Is there some historical significance to why there are the two names?




What is the difference between gmake and make?

For variable assignment in Make, I see := and = operator. What&#39;s the difference between them? 

What&#39;s the difference between := and = in Makefile?

How can I check if a program is callable from a Makefile?

(That is, the program should exist in the path or otherwise be callable.) 

It could be used to check for which compiler is installed, for instance.

E.g. something like [this question][1], but without assuming the underlying shell is POSIX compatible.


  [1]: https://stackoverflow.com/questions/592620/check-if-a-program-exists-from-a-bash-script

Check if a program exists from a Makefile

It&#39;s been a while since I&#39;ve used `make`, so bear with me...

I&#39;ve got a directory, `flac`, containing .FLAC files. I&#39;ve got a corresponding directory, `mp3` containing MP3 files. If a FLAC file is newer than the corresponding MP3 file (or the corresponding MP3 file doesn&#39;t exist), then I want to run a bunch of commands to convert the FLAC file to an MP3 file, and copy the tags across.

The kicker: I need to search the `flac` directory recursively, and create corresponding subdirectories in the `mp3` directory. The directories and files can have spaces in the names, and are named in UTF-8.

And I want to use `make` to drive this.


Recursive wildcards in GNU make?

There seems to be some controversy on whether the number of jobs in GNU make is supposed to be equal to the number of cores, or if you can optimize the build time by adding one extra job that can be queued up while the others &quot;work&quot;.

Is it better to use `-j4` or `-j5` on a quad core system?

Have you seen (or done) any benchmarking that supports one or the other?

GNU make: should the number of jobs equal the number of CPU cores in a system?

I have a fairly large makefile that creates a number of targets on the fly by computing names from variables. (eg foo$(VAR) : $(PREREQS)).  Is there any way that gnu make can be convinced to spit out a list of targets after it has expanded these variables?

I&#39;d like to be able to get the targets for an aribitrary makefile.  I&#39;m trying to write a completion function for my shell.

List goals/targets in GNU make that contain variables in their definition

I installed MinGW and MSYS, added `C:\MinGW\bin` to `PATH` but I still can&#39;t run Makefile on Windows&#39; `cmd`. I would like to run cmd.exe and there type, for example, `make all` but my cmd says that there is no such command. 

What should I do? I don&#39;t want to use MSYS shell, that&#39;s not the point. Any ideas how to use GNU Make in Windows cmd as I can do it in Ubuntu? I&#39;m not interested in `Cygwin`.

How to use GNU Make on Windows?

In a GNU makefile, I am wondering if it is possible, with an file list input, to make a file list output with new extensions.

In input, I get this list:

    FILES_IN=file1.doc file2.xls

And I would like to build this variable in my makefile from **FILES_IN** variable:

    FILES_OUT=file1.docx file2.xlsx

Is it possible ? How ?

It&#39;s quite difficult because I have to parse file list, and detect each extension (.doc, .xls) to replace it to correct extension.




How to change the extension of each file in a list with multiple extensions in GNU make?

I have a makefile, which includes several other makefiles, which in turn all add to a variable like this:

    VAR := Something SomethingElse
    VAR += SomeOtherThing
    
    (...)

Now I wish to remove `SomethingElse` from the `VAR` variable. What do I put in place of `(...)` to do this?

I am using GNU Make, and a GNU Make specific solution will be fine.

Remove item from a Makefile variable?

&gt; **Possible Duplicate:**  
&gt; [Make error: missing separator](https://stackoverflow.com/questions/920413/make-error-missing-separator)  

&lt;!-- End of automatically inserted text --&gt;

Have this code in makefile:

    PROG = semsearch
    all: $(PROG)
    %: %.c
    gcc -o $@ $&lt; -lpthread
    
    clean:
    rm $(PROG)

and the error

    missing separator. stop.

Can someone help me?

Makefile - missing separator

&gt; **Possible Duplicate:**  
&gt; https://stackoverflow.com/questions/448910/makefile-variable-assignment

&lt;!-- End of automatically inserted text --&gt;

I only know very basic `makefile` syntax, and was reading through another project&#39;s `makefile` and came across `:=` for macro declaration. Why would they use that?

In other words, is there any difference between

    MYMACRO = hi i&#39;m a macro

and

    MYMACRO := hi i&#39;m a macro
?

:= vs = in make macros

I have a directory (`root_dir`), that contains a number of sub-directories (`subdir1, subdir2, ...`).

I want to run the `make` in each directory in `root_dir`, using  a Makefile placed in it.
(Obviously supposed that each of `subdir...` has inside its own Makefile).

So there are essentially two questions:

 1. How to get a list of directories in Makefile (automatically)?
 2. How to run `make` for each of the directories inside a make file?

As I know in order to run `make` in a specific directory I need to do the following:

    $(MAKE) -C subdir

Run make in each subdirectory

I&#39;m working on a large C++ project built with CMake on Linux.  CMake runs okay, producing a horde of Makefiles in the tree of modules and applications. Running GNU `make` leads to linker errors.  How can I get `make` to print out the exact commands before running them?

The -d option does not print the commands, but plenty of information that hasn&#39;t been helpful.

The -n option prints all the commands, but does not run them, so I can&#39;t tell were exactly the trouble is. Examining the stdout from make -n, I don&#39;t see any commands that are relevant. I suspect some commands change depending on the results of earlier commands, and the hierarchy of Makefiles makes it difficult to tell what&#39;s really going on.

I don&#39;t see any other options in make&#39;s *man* page that seem helpful.



Making CMake print commands before executing

Is there a command line way in `make` to find out which of the prerequisites of a target is not updated?

Debugging GNU make

I&#39;m having trouble with trying to use make to place object files in a separate subdirectory, probably a very basic technique. I have tried to use the information in this page:
&lt;http://www.gnu.org/software/hello/manual/make/Prerequisite-Types.html#Prerequisite-Types&gt;

I get the following output from make:

    make: *** No rule to make target `ku.h&#39;, needed by `obj/kumain.o&#39;.  Stop.

However ku.h is a dependency not a target (although it&#39;s obviously #included within the c source files). When I don&#39;t try to use a subdirectory for object files (i.e. miss out the OBJDIR parts) it works fine. Why does make think ku.h is a target?

my makefile is this: (the style is after reading various sources of information)

    .SUFFIXES:
    .SUFFIXES: .c .o

    CC=gcc 
    CPPFLAGS=-Wall
    LDLIBS=-lhpdf
    VPATH=%.c src
    VPATH=%.h src
    VPATH=%.o obj
    OBJDIR=obj

    objects= $(addprefix $(OBJDIR)/, kumain.o kudlx.o kusolvesk.o kugetpuz.o kuutils.o \
      kurand.o kuASCboard.o kuPDFs.o kupuzstrings.o kugensud.o \
      kushapes.o )

    ku : $(objects)
      $(CC) $(CPPFLAGS) -o ku $(objects) $(LDLIBS)
  
    $(objects) : ku.h kudefines.h kuglobals.h kufns.h | $(OBJDIR)
         
    $(OBJDIR):
      mkdir $(OBJDIR)

    .PHONY: clean
    clean :
      rm $(objects)
Edit:
I applied the change to use the vpath directive. My version was a bad mixture of VPATH=xxx and vpath %.c xxx. However I now get another problem (which was the original problem before I added the wrong vpath). This is now the output:

		gcc  -o ku -lhpdf obj/kumain.o obj/kudlx.o obj/kusolvesk.o ..etc
		gcc: obj/kumain.o: No such file or directory
		gcc: obj/kudlx.o: No such file or directory
		gcc: obj/kusolvesk.o: No such file or directory
		gcc: obj/kugetpuz.o: No such file or directory
		gcc: obj/kuutils.o: No such file or directory
		gcc: obj/kurand.o: No such file or directory
		gcc: obj/kuASCboard.o: No such file or directory
		gcc: obj/kuPDFs.o: No such file or directory
		gcc: obj/kupuzstrings.o: No such file or directory
		gcc: obj/kugensud.o: No such file or directory
		gcc: obj/kushapes.o: No such file or directory
		make: *** [ku] Error 1

It appears that make is not applying the implicit rule for an object file although the manual says 
&quot;Implicit rules tell make how to use customary techniques so that you do not have to specify them in detail when you want to use them. For example, there is an implicit rule for C compilation. File names determine which implicit rules are run. For example, C compilation typically takes a .c file and makes a .o file. So make applies the implicit rule for C compilation when it sees this combination of file name endings.&quot; and also &quot;The search through the directories specified in VPATH or with vpath also happens during consideration of implicit rules (see Using Implicit Rules).&quot;

Again here &quot;For example, when a file foo.o has no explicit rule, make considers implicit rules, such as the built-in rule to compile foo.c if that file exists. If such a file is lacking in the current directory, the appropriate directories are searched for it. If foo.c exists (or is mentioned in the makefile) in any of the directories, the implicit rule for C compilation is applied.&quot;

Any assistance in getting implicit rules to work for my makefile would be greatly appreciated.

Edit no 2:
Thanks to Jack Kelly I have made an explicit rule to compile the .c files since I couldn&#39;t get anywhere trying to use implicit rules. Also thanks to al_miro for the vpath info.

Here is the working makfile:

    .SUFFIXES:
    .SUFFIXES: .c .o

    CC=gcc 
    CPPFLAGS=-Wall
    LDLIBS=-lhpdf
    OBJDIR=obj
    vpath %.c src
    vpath %.h src

    objects = $(addprefix $(OBJDIR)/, kumain.o kudlx.o kusolvesk.o kugetpuz.o kuutils.o \
      kurand.o kuASCboard.o kuPDFs.o kupuzstrings.o kugensud.o \
      kushapes.o )

    ku : $(objects)
      $(CC) $(CPPFLAGS) -o ku $(objects) $(LDLIBS)
  
    $(OBJDIR) obj/%.o : %.c ku.h kudefines.h kuglobals.h kufns.h 
      $(CC) -c $(CPPFLAGS) $&lt; -o $@

    .PHONY : clean
    clean :
      rm $(objects)



How to place object files in separate subdirectory

I want to detect a condition in my makefile where a tool is the wrong version and force the make to fail with an error message indicating the item is not the right version.

Can anyone give an example of doing this?

I tried the following but it is not the right syntax:

    ifeq &quot;$(shell svnversion --version | sed s/[^0-9\.]*://)&quot; &quot;1.4&quot;
    $error(&quot;Bad svnversion v1.4, please install v1.6&quot;)
    endif


Thanks.

How to force an error in a gnumake file

I am using a GNU-make Makefile to build a C project with several targets (`all`, `clean`, and a few project specific targets). In the process of debugging, I would like to append some flags to a single build without permanently editing the Makefile (e.g. add debugging symbols or set a preprocessor flag).

In the past, I have done that as follows (using the debugging symbols example):

    make target CFLAGS+=-g

Unfortunately, this is not appending to the `CFLAGS` variable, but instead, clearing it and stopping it from compiling. Is there a clean way of doing this without defining some sort of dummy variable appended to the end of `CFLAGS` and `LDFLAGS`?

Append to GNU make variables via command line

I want to disable builtin rules and variables as per passing the [`-r` and `-R` options][1] to GNU make, from inside the make file. Other solutions that allow me to do this implicitly and transparently are also welcome.

I&#39;ve found [several references][2] to using [`MAKEFLAGS`][3], and had similar problems.


  [1]: http://www.gnu.org/software/make/manual/make.html#Options-Summary
  [2]: http://blog.electric-cloud.com/2009/08/19/makefile-performance-built-in-rules/#comment-219
  [3]: http://www.gnu.org/software/make/manual/make.html#Quick-Reference

Disable make builtin rules and variables from inside the make file

Recently, I switched my development environment from Windows to Linux. So far, I have only used Visual Studio for C++ development, so many concepts, like [make][1] and [Autotools][2], are new to me. I have read the GNU makefile documentation and got almost an idea about it. But I am kind of confused about Autotools.

As far as I know, makefiles are used to make the build process easier.

 1. Why do we need tools like *Autotools* just for creating the makefiles? Since all knows how to create a makefile, I am not getting the real use of Autotools.
 2. What is the standard? Do we need to use tools like this or would just handwritten makefiles do?

  [1]: http://en.wikipedia.org/wiki/Make_%28software%29
  [2]: http://en.wikipedia.org/wiki/GNU_build_system


Why use build tools like Autotools when we can just write our own makefiles?

After years of not using make, I find myself needing it again, the gnu version now.  I&#39;m pretty sure I should be able to do what I want, but haven&#39;t figured out how, or found an answer with Google, etc.

I&#39;m trying to create a test target which will execute my program a number of times, saving the results in a log file.  Some tests should cause my program to abort.  Unfortunately, my makefile aborts on the first test which leads to an error.  I have something like:

    # Makefile
    # 
    test:
            myProg -h &gt; test.log              # Display help
            myProg good_input &gt;&gt; test.log     # should run fine
            myProg bad_input1 &gt;&gt; test.log      # Error 1
            myProg bad_input2 &gt;&gt; test.log      # Error 2

With the above, make quits after the bad_input1 run, never getting to the bad_input2 run.






How to have GNU make explicitly test for failure?

One rule in my Makefile zips an entire directory (`res/`) into a ZIP file. Obviously, this rule needs to execute when *any* file under the `res/` directory changes. Thus, I want the rule to have as a prerequisite all files underneath that directory. How can I implement this rule?

In Bash [with the `globstar` option enabled](https://unix.stackexchange.com/questions/49913/recursive-glob/49917#49917), you can obtain a list of all the files in that directory using the wildcard pattern `res/**/*`. However, it doesn&#39;t seem to work if you specify it as a prerequisite in the Makefile:

    filename.jar: res/**/*

Even after `touch`ing a file in `res/`, Make still reports

    make: `filename.jar&#39; is up to date.

so clearly it is not recognizing the pattern.

If I declare the directory itself as a prerequisite:

    filename.jar: res

then Make will not re-execute when a file is modified (I think `make` only looks at the modified date of the directory itself, which only changes when immediate children are added, removed, or renamed).

Makefile rule that depends on all files under a directory (including within subdirectories)

How can I compact the folllowing Makefile targets?

    $(GRAPHDIR)/Complex.png: $(GRAPHDIR)/Complex.dot
            dot $(GRAPHDIR)/Complex.dot -Tpng -o $(GRAPHDIR)/Complex.png
    
    $(GRAPHDIR)/Simple.png: $(GRAPHDIR)/Simple.dot
            dot $(GRAPHDIR)/Simple.dot -Tpng -o $(GRAPHDIR)/Simple.png
    
    $(GRAPHDIR)/IFileReader.png: $(GRAPHDIR)/IFileReader.dot
            dot $(GRAPHDIR)/IFileReader.dot -Tpng -o $(GRAPHDIR)/IFileReader.png
    
    $(GRAPHDIR)/McCabe-linear.png: $(GRAPHDIR)/McCabe-linear.dot
            dot $(GRAPHDIR)/McCabe-linear.dot -Tpng -o $(GRAPHDIR)/McCabe-linear.png
    
    graphs: $(GRAPHDIR)/Complex.png $(GRAPHDIR)/Simple.png $(GRAPHDIR)/IFileReader.png $(GRAPHDIR)/McCabe-linear.png

--

Using `GNU Make 3.81`.

Wildcard targets in a Makefile

I am trying to force make file to display next string:

    &quot;Please execute next commands:
    setenv PATH /usr/local/greenhills/mips5/linux86:$PATH&quot;

The problem is with `&quot;$PATH&quot;`. Command

    @echo &quot;setenv PATH /usr/local/greenhills/mips5/linux86:$PATH&quot;

cause a result
    

    &quot;setenv PATH /usr/local/greenhills/mips5/linux86:ATH&quot;

any combinations of escape characters, quotes, `&quot;$(shell echo &quot;` didn&#39;t get required results...

Any suggestions? 

Make file echo displaying &quot;$PATH&quot; string

Ever since I learned about -j I&#39;ve used -j8 blithely.  The other day I was compiling an atlas installation and the make failed.  Eventually I tracked it down to things being made out of order - and it worked fine once I went back to singlethreaded make.  This makes me nervous.  What sort of conditions do I need to watch for when writing my own make files to avoid doing something unexpected with make -j?

GNU make&#39;s -j option

Usually kernel source are stored in `/usr/src/linux-2.6.x/`.
To avoid to recompile the entire kernel if I modify a module&#39;s source, how can I recompile just that module?

How to recompile just a single kernel module?

For various reasons, it would be convenient for me to specify .PHONY in multiple parts of a makefile. I feel like I&#39;m not correctly understanding how this works, but is this possible?

Instead of `.PHONY: clean cleanall`
do:

    .PHONY: clean
    &lt;some text&gt;
    .PHONY: cleanall

Is it possible to have multiple .PHONY targets in a GNU makefile?

I need to get the nth dependency file from a rule, something similar to $n in bash. I need this because I&#39;d like to feed in individual dependency files as options to the build program.

Here&#39;s an example:

    dep.o: dep.src config1.cfg config2.cfg
        parse -cfg1 $2 -cfg2 $3 -o $@ $&lt;

Is it possible?

How to get the second dependency file using Automatic Variables in a Makefile?

I know that the `@` prefix suppresses output from a shell command in Makefiles, and also that the `-` prefix will ignore errors from a shell command. Is there a way to combine the two, i.e. a prefix that suppresses output and ignores errors? I don&#39;t think `@-` or `-@` works.

Suppress and ignore output for Makefile?

I am writing a Makefile with a lot of repetitive stuff, e.g.

    debug_ifort_Linux:
            if [ $(UNAME) = Linux ]; then                           \
              $(MAKE) FC=ifort FFLAGS=$(difort) PETSC_FFLAGS=&quot;...&quot;  \
                      TARGET=$@ LEXT=&quot;ifort_$(UNAME)&quot; -e syst;      \
            else                                                    \
              echo $(err_arch);                                     \
              exit 1;                                               \
            fi

where the target &#39;syst&#39; is defined, the variable &#39;UNAME&#39; is defined (and is usually Linux, but might also by Cygwin or OSF1) and the variables &#39;difort&#39; and &#39;err_arch&#39; are also defined. This block of code is used very many times for different compiler targets (using a name convention of &#39;&lt;debug|profile|optim&gt;_&lt;compiler&gt;_&lt;uname&gt;&#39;). Since this is a huge amount of redundant code, I would like to be able to write it in a more simple manner. E.g., I would like to do something like this:

    debug_ifort_Linux:
            compile(uname,compiler,flags,petsc_flags,target,lext)

where compile could be a function doing the code above based on the arguments. Does anyone have any idea how I could accomplish this?

Functions in Makefile

How to get the invoking target of the GNU make Makefile?

for example, I invoke `make` with the following command line:

    make a-target

How can I get the invoking target &quot;a-target&quot; in the Makefile and assign it to a variable?

Further more, if more than one target is specified on the command line:

    make target1 target2 ...

How do I get all of them?

How to get the invoking target of makefile?

How can I list the current value of all variables (also called macros) in a Makefile when running make?

E.g. if this is in the Makefile:

    CUR-DIR := $(shell /bin/pwd)
    LOG-DIR := $(CUR-DIR)/make-logs

Then I would like it to tell me:

    CUR-DIR = /home/johv/src/test
    LOG-DIR = /home/johv/src/test/make-logs


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