Disable make builtin rules and variables from inside the make file

BuildMakefileGnuGnu Make

Build Problem Overview

I want to disable builtin rules and variables as per passing the -r and -R options to GNU make, from inside the make file. Other solutions that allow me to do this implicitly and transparently are also welcome.

I've found several references to using MAKEFLAGS, and had similar problems.

Build Solutions

Solution 1 - Build

Disabling the built-in rules is done by writing an empty rule for .SUFFIXES:


Having erased the built-in rules, I'm not sure that erasing the built-in variables helps you much more than just remembering to set them yourself or not use them, but you could use something like

$(foreach V,
    $(shell make -p -f/dev/null 2>/dev/null | sed -n '/^[^:#= ]* *=/s/ .*//p'),
    $(if $(findstring default,$(origin $V)),$(eval $V=)))

...which is admittedly fairly crazy. If there is a way to get a list of the defined variables from within make (instead of shelling out to another make), it would be viable. As it is, it's not really much better than

# etc, for each likely built-in variable

Solution 2 - Build

@hseldon has the right idea because .SUFFIXES doesn't cover the match-everything built-in implicit rules. However, I don't think his syntax is exactly right.

MAKEFLAGS += --no-builtin-rules

.SUFFIXES: .you .own .here

See http://www.gnu.org/software/make/manual/make.html#Match_002dAnything-Rules and http://www.gnu.org/software/make/manual/make.html#index-g_t_002eSUFFIXES-998

Solution 3 - Build


# Disable built-in rules and variables
MAKEFLAGS += --no-builtin-rules
MAKEFLAGS += --no-builtin-variables

# Makefile begins
main: main.c
    cc main.c -o main

Solution 4 - Build

Disabling of built-in rules by writing an empty rule for .SUFFIXES does not work if one then writes another .SUFFIXES rule to add previously known suffixes - the built-in rules are re-enabled. Example: One wants to define rules for .c.i and .i.o, and to disable the built-in rule .c.o. Writing

.SUFFIXES: .o .i .c

does not work - it does not prevent the built-in rule .c.o from being applied.

The solution is the one employed by Marc Eaddy and documented in the GNU make manual, 10.5.6 Canceling Implicit Rules:

> You can override a built-in implicit rule (or one you have defined > yourself) by defining a new pattern rule with the same target and > prerequisites, but a different recipe. When the new rule is defined, > the built-in one is replaced. The new rule’s position in the sequence > of implicit rules is determined by where you write the new rule. > > You can cancel a built-in implicit rule by defining a pattern rule > with the same target and prerequisites, but no recipe. For example, > the following would cancel the rule that runs the assembler: > > %.o : %.s

Solution 5 - Build

This works for me:

# Disable implicit rules to speedup build
%: %.o
%: %.c
%.ln: %.c
%.o: %.c
%: %.cc
%.o: %.cc
%: %.C
%.o: %.C
%: %.cpp
%.o: %.cpp
%: %.p
%.o: %.p
%: %.f
%.o: %.f
%: %.F
%.o: %.F
%.f: %.F
%: %.r
%.o: %.r
%.f: %.r
%.ln: %.y
%.c: %.y
%.ln: %.l
%.c: %.l
%.r: %.l
%: %.s
%.o: %.s
%: %.S
%.o: %.S
%.s: %.S
%: %.mod
%.o: %.mod
%.sym: %.def
%.dvi: %.tex
%.info: %.texinfo
%.dvi: %.texinfo
%.info: %.texi
%.dvi: %.texi
%.info: %.txinfo
%.dvi: %.txinfo
%.c: %.w
%.tex: %.w
%.p: %.web
%.tex: %.web
%: %.sh
(%): %
%.out: %
%.c: %.w %.ch
%.tex: %.w %.ch
%: %,v
%: RCS/%,v
%: RCS/%
%: s.%
%: SCCS/s.%

Put this in a file named disable_implicit_rules.mk and include it in every makefile.

Solution 6 - Build

You could start the Makefile with a #! and call it something different so people don't try to use make directly:

#!/usr/bin/make -rRf
# ...

This will cause horrific problems if GNU make is not the system make. Maybe a wrapper script?

You can also read $(MAKEFLAGS) and make sure the required flags are present.

Solution 7 - Build


Solution 8 - Build

Do this:

$(foreach x,$(filter-out .% MAKE% SHELL CURDIR,$(.VARIABLES)) MAKEINFO,$(if $(filter default,$(origin $x)),$(eval override undefine $x)))

Here, rR is equivalent to --no-builtin-rules --no-builtin-variables.

--no-builtin-rules seems to work properly, but --no-builtin-variables is wonky.

--no-builtin-variables prevents the recipes from seeing the variables, but if you try to access them outside of a recipe, they are still there.

That's what the second line is for. It manually undefines all built-in variables. (Same idea as in @JohnMarshall's answer, but without shell invocations.)

It removes all variables for which $(origin ) reports default, except that it ignores SHELL,CURDIR, and variables starting with . and MAKE (except MAKEINFO), since those look useful.


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Content TypeOriginal AuthorOriginal Content on Stackoverflow
QuestionMatt JoinerView Question on Stackoverflow
Solution 1 - BuildJohn MarshallView Answer on Stackoverflow
Solution 2 - BuildBrandon BloomView Answer on Stackoverflow
Solution 3 - BuildJaakkoView Answer on Stackoverflow
Solution 4 - BuildArmaliView Answer on Stackoverflow
Solution 5 - BuildMarc EaddyView Answer on Stackoverflow
Solution 6 - BuildJack KellyView Answer on Stackoverflow
Solution 7 - BuildhseldonView Answer on Stackoverflow
Solution 8 - BuildHolyBlackCatView Answer on Stackoverflow