Yes, that&#39;s allowed. (If you don&#39;t believe me, just try it!)

    PHONY= 
    PHONY+= clean
    
    ...
    
    PHONY+= cleanall
    .PHONY : $(PHONY)



I use a code where I cast an enum* to int*. Something like this:

    enum foo { ... }
    ...
    foo foobar;
    int *pi = reinterpret_cast&lt;int*&gt;(&amp;foobar);

 When compiling the code (g++ 4.1.2), I get the following warning message:

    dereferencing type-punned pointer will break strict-aliasing rules

I googled this message, and found that it happens only when strict aliasing optimization is on. I have the following questions:

 - If I leave the code with this warning, will it generate potentially wrong code?
 - Is there any way to work around this problem?
 - If there isn&#39;t, is it possible to turn off strict aliasing from inside the source file (because I don&#39;t want to turn it off for all source files and I don&#39;t want to make a separate Makefile rule for this source file)?

And yes, I actually need this kind of aliasing.

&quot;dereferencing type-punned pointer will break strict-aliasing rules&quot; warning

What do the curly braces surrounding JavaScript arguments for functions do? 

    var port = chrome.extension.connect({name: &quot;testing&quot;});
    port.postMessage({found: (count != undefined)});



Curly braces inside JavaScript arguments for functions

For various reasons, it would be convenient for me to specify .PHONY in multiple parts of a makefile. I feel like I&#39;m not correctly understanding how this works, but is this possible?

Instead of `.PHONY: clean cleanall`
do:

    .PHONY: clean
    &lt;some text&gt;
    .PHONY: cleanall

Is it possible to have multiple .PHONY targets in a GNU makefile?

For various reasons, it would be convenient for me to specify .PHONY in multiple parts of a makefile. I feel like I'm not correctly understanding how this works, but is this possible?
Instead of <code>.PHONY: clean cleanall</code>
do:
<pre><code class="hljs language-makefile">.PHONY: clean
&#x3C;some text>
.PHONY: cleanall
</code></pre>

Can anyone explain what the target &quot;oldconfig&quot; does exactly in the Linux kernel makefile?  I see it referenced in some build documentation but never explained what it does exactly.

What does &quot;make oldconfig&quot; do exactly in the Linux kernel makefile?

Suppose I have a simple makefile like:

    hello:
       echo &quot;hello world&quot;
    
    bye:
       echo &quot;bye bye&quot;

Then in bash I want something like:

&gt; make h &lt; tab &gt;

so it can complete to

&gt; make hello

I found a simple way like creating empty files `hello` and `bye` but I&#39;m looking for something more _sophisticated_.

bash completion of makefile target

I&#39;ve used rake a bit (a Ruby make program), and it has an option to get a list of all the available targets, eg

    &gt; rake --tasks
    rake db:charset      # retrieve the charset for your data...
    rake db:collation    # retrieve the collation for your da...
    rake db:create       # Creates the databases defined in y...
    rake db:drop         # Drops the database for your curren...
    ...

but there seems to be no option to do this in GNU make. 

Apparently the code is almost there for it, as of 2007 - http://www.mail-archive.com/help-make@gnu.org/msg06434.html. 

Anyway, I made little hack to extract the targets from a makefile, which you can include in a makefile. 

    list:
        @grep &#39;^[^#[:space:]].*:&#39; Makefile

It will give you a list of the defined targets. It&#39;s just a start - it doesn&#39;t filter out the dependencies, for instance. 

    &gt; make list
    list:
    copy:
    run:
    plot:
    turnin:



How do you get the list of targets in a makefile?

I&#39;m writing a Makefile that does string matching at one place, the code is like:

    if test ...; \
        then \
        shell scripts... \
    fi
    
    ifeq ($(DIST_TYPE),nightly)
        shell scripts ...
    endif

Here the first `if` is shell script, the second `ifeq` is GNU Make&#39;s conditional. However the following error generates:

&gt; ifeq (nightly,nightly)
&gt; 
&gt; /bin/sh: -c: line 0: syntax error near unexpected token `nightly,nightly&#39;
&gt; 
&gt; /bin/sh: -c: line 0: `ifeq (nightly,nightly)&#39;

What&#39;s happening here? It seems that Make is trying to call the shell.

Make error for ifeq: syntax error near unexpected token

Is there a way to comment out multiple lines in makefiles like as in C syntax `/* */` ?

How to add multi line comments in makefiles

I&#39;m working on a large C++ project built with CMake on Linux.  CMake runs okay, producing a horde of Makefiles in the tree of modules and applications. Running GNU `make` leads to linker errors.  How can I get `make` to print out the exact commands before running them?

The -d option does not print the commands, but plenty of information that hasn&#39;t been helpful.

The -n option prints all the commands, but does not run them, so I can&#39;t tell were exactly the trouble is. Examining the stdout from make -n, I don&#39;t see any commands that are relevant. I suspect some commands change depending on the results of earlier commands, and the hierarchy of Makefiles makes it difficult to tell what&#39;s really going on.

I don&#39;t see any other options in make&#39;s *man* page that seem helpful.



Making CMake print commands before executing

For variable assignment in Make, I see := and = operator. What&#39;s the difference between them? 

What&#39;s the difference between := and = in Makefile?

I&#39;m having trouble with trying to use make to place object files in a separate subdirectory, probably a very basic technique. I have tried to use the information in this page:
&lt;http://www.gnu.org/software/hello/manual/make/Prerequisite-Types.html#Prerequisite-Types&gt;

I get the following output from make:

    make: *** No rule to make target `ku.h&#39;, needed by `obj/kumain.o&#39;.  Stop.

However ku.h is a dependency not a target (although it&#39;s obviously #included within the c source files). When I don&#39;t try to use a subdirectory for object files (i.e. miss out the OBJDIR parts) it works fine. Why does make think ku.h is a target?

my makefile is this: (the style is after reading various sources of information)

    .SUFFIXES:
    .SUFFIXES: .c .o

    CC=gcc 
    CPPFLAGS=-Wall
    LDLIBS=-lhpdf
    VPATH=%.c src
    VPATH=%.h src
    VPATH=%.o obj
    OBJDIR=obj

    objects= $(addprefix $(OBJDIR)/, kumain.o kudlx.o kusolvesk.o kugetpuz.o kuutils.o \
      kurand.o kuASCboard.o kuPDFs.o kupuzstrings.o kugensud.o \
      kushapes.o )

    ku : $(objects)
      $(CC) $(CPPFLAGS) -o ku $(objects) $(LDLIBS)
  
    $(objects) : ku.h kudefines.h kuglobals.h kufns.h | $(OBJDIR)
         
    $(OBJDIR):
      mkdir $(OBJDIR)

    .PHONY: clean
    clean :
      rm $(objects)
Edit:
I applied the change to use the vpath directive. My version was a bad mixture of VPATH=xxx and vpath %.c xxx. However I now get another problem (which was the original problem before I added the wrong vpath). This is now the output:

		gcc  -o ku -lhpdf obj/kumain.o obj/kudlx.o obj/kusolvesk.o ..etc
		gcc: obj/kumain.o: No such file or directory
		gcc: obj/kudlx.o: No such file or directory
		gcc: obj/kusolvesk.o: No such file or directory
		gcc: obj/kugetpuz.o: No such file or directory
		gcc: obj/kuutils.o: No such file or directory
		gcc: obj/kurand.o: No such file or directory
		gcc: obj/kuASCboard.o: No such file or directory
		gcc: obj/kuPDFs.o: No such file or directory
		gcc: obj/kupuzstrings.o: No such file or directory
		gcc: obj/kugensud.o: No such file or directory
		gcc: obj/kushapes.o: No such file or directory
		make: *** [ku] Error 1

It appears that make is not applying the implicit rule for an object file although the manual says 
&quot;Implicit rules tell make how to use customary techniques so that you do not have to specify them in detail when you want to use them. For example, there is an implicit rule for C compilation. File names determine which implicit rules are run. For example, C compilation typically takes a .c file and makes a .o file. So make applies the implicit rule for C compilation when it sees this combination of file name endings.&quot; and also &quot;The search through the directories specified in VPATH or with vpath also happens during consideration of implicit rules (see Using Implicit Rules).&quot;

Again here &quot;For example, when a file foo.o has no explicit rule, make considers implicit rules, such as the built-in rule to compile foo.c if that file exists. If such a file is lacking in the current directory, the appropriate directories are searched for it. If foo.c exists (or is mentioned in the makefile) in any of the directories, the implicit rule for C compilation is applied.&quot;

Any assistance in getting implicit rules to work for my makefile would be greatly appreciated.

Edit no 2:
Thanks to Jack Kelly I have made an explicit rule to compile the .c files since I couldn&#39;t get anywhere trying to use implicit rules. Also thanks to al_miro for the vpath info.

Here is the working makfile:

    .SUFFIXES:
    .SUFFIXES: .c .o

    CC=gcc 
    CPPFLAGS=-Wall
    LDLIBS=-lhpdf
    OBJDIR=obj
    vpath %.c src
    vpath %.h src

    objects = $(addprefix $(OBJDIR)/, kumain.o kudlx.o kusolvesk.o kugetpuz.o kuutils.o \
      kurand.o kuASCboard.o kuPDFs.o kupuzstrings.o kugensud.o \
      kushapes.o )

    ku : $(objects)
      $(CC) $(CPPFLAGS) -o ku $(objects) $(LDLIBS)
  
    $(OBJDIR) obj/%.o : %.c ku.h kudefines.h kuglobals.h kufns.h 
      $(CC) -c $(CPPFLAGS) $&lt; -o $@

    .PHONY : clean
    clean :
      rm $(objects)



How to place object files in separate subdirectory

How can I check if a program is callable from a Makefile?

(That is, the program should exist in the path or otherwise be callable.) 

It could be used to check for which compiler is installed, for instance.

E.g. something like [this question][1], but without assuming the underlying shell is POSIX compatible.


  [1]: https://stackoverflow.com/questions/592620/check-if-a-program-exists-from-a-bash-script

Content Type	Original Author	Original Content on Stackoverflow
Question	wickedchicken	View Question on Stackoverflow
Solution 1 - Makefile	Beta	View Answer on Stackoverflow
Solution 2 - Makefile	STyx	View Answer on Stackoverflow

Is it possible to have multiple .PHONY targets in a GNU makefile?

Makefile Problem Overview

Makefile Solutions

Solution 1 - Makefile

Solution 2 - Makefile

Curly braces inside JavaScript arguments for functions

"dereferencing type-punned pointer will break strict-aliasing rules" warning

Attributions