The variable [`MAKECMDGOALS`](https://www.gnu.org/software/make/manual/html_node/Goals.html) contains the list of targets that were specified on the command line, no matter how many (it&#39;s empty if there were none).

Maybe you need `$@`?

See http://www.gnu.org/software/make/manual/make.html#Automatic-Variables for more details.

This might have been asked a million times before or might be incredibly stupid but why is it not implemented?

    class A
    {
          public:
                 A(){ a = 5;}
                 int a;
    };
    
    class B:public A
    {
          public:
                 B(){ a = 0.5;}
                  float a;
    };
    
    int main()
    {
        A * a = new B();
        
        cout&lt;&lt;a-&gt;a;
        getch();
        return 0;
    }

This code will access A::a. How do I access B::a? 

Why doesn&#39;t C++ have virtual variables?

I am using a SQLite database and would like to speed up my queries, perhaps with indexes or by restructuring them altogether.

Is there a tool to profile queries, that might help me decide where things are slowing down?

I know I could just enter queries into a tool like SQLite Administrator to time them, but I&#39;m looking for something a bit more systematic than that -- perhaps something that sits in the background and looks at all the queries that I enter over a period, giving a breakdown of any bottle necks.

Is there a tool to profile sqlite queries?

How to get the invoking target of the GNU make Makefile?

for example, I invoke `make` with the following command line:

    make a-target

How can I get the invoking target &quot;a-target&quot; in the Makefile and assign it to a variable?

Further more, if more than one target is specified on the command line:

    make target1 target2 ...

How do I get all of them?

How to get the invoking target of makefile?

How to get the invoking target of the GNU make Makefile?
for example, I invoke <code>make</code> with the following command line:
<pre><code class="hljs language-css">make a-target
</code></pre>
How can I get the invoking target "a-target" in the Makefile and assign it to a variable?
Further more, if more than one target is specified on the command line:
<pre><code class="hljs language-go">make target1 target2 ...
</code></pre>
How do I get all of them?

    CC=g++
    CFLAGS=-c -Wall
    LDFLAGS=
    SOURCES=main.cpp hello.cpp factorial.cpp
    OBJECTS=$(SOURCES:.cpp=.o)
    EXECUTABLE=hello

    all: $(SOURCES) $(EXECUTABLE)
	
    $(EXECUTABLE): $(OBJECTS)
    	$(CC) $(LDFLAGS) $(OBJECTS) -o $@

    .cpp.o:
        $(CC) $(CFLAGS) $&lt; -o $@

What do the `$@` and `$&lt;` do exactly?

What do the makefile symbols $@ and $&lt; mean?

I want to run &#39;make install&#39; so I have everything I need, but I&#39;d like it to install the things in their own folder as opposed to the system&#39;s /usr/bin etc. is that possible? even if it references tools in the /usr/bin etc.? 

Make install, but not to default directories?

I have a makefile structured something like this:

    all : 
        compile executable

    clean :
        rm -f *.o $(EXEC)

I realized that I was consistently running &quot;make clean&quot; followed by &quot;clear&quot; in my terminal before running &quot;make all&quot;. I like to have a clean terminal before I try and sift through nasty C++ compilation errors. So I tried to add a 3rd target:

    fresh :
        rm -f *.o $(EXEC)
        clear
        make all

This works, however this runs a second instance of make (I believe). Is there a right way to get the same functionality without running a 2nd instance of make?

makefile execute another target

Can somebody please enlighten me as to what the command line flag to CMake might be that will make it print out all the compile/link commands it executes?

I can&#39;t find this anywhere in the documentation. Many hours of my life have just evaporated. I&#39;d just like to verify it&#39;s doing what I think it is, (then banish the infernal build system altogether and replace it with a GNU Makefile).
Thank you!


cmake, print compile/link commands

In the GNU Makefile manual, it [mentions][1] these prefixes.

&gt; If .ONESHELL is provided, then only the first line of the recipe will be checked for the special prefix characters (‘@’, ‘-’, and ‘+’).

What do these prefixes do, and where are they mentioned?

  [1]: http://www.gnu.org/software/make/manual/make.html#One-Shell

What do @, - and + do as prefixes to recipe lines in Make?

I want to disable builtin rules and variables as per passing the [`-r` and `-R` options][1] to GNU make, from inside the make file. Other solutions that allow me to do this implicitly and transparently are also welcome.

I&#39;ve found [several references][2] to using [`MAKEFLAGS`][3], and had similar problems.


  [1]: http://www.gnu.org/software/make/manual/make.html#Options-Summary
  [2]: http://blog.electric-cloud.com/2009/08/19/makefile-performance-built-in-rules/#comment-219
  [3]: http://www.gnu.org/software/make/manual/make.html#Quick-Reference

Disable make builtin rules and variables from inside the make file

I have a textfile, containing something like:

    12,34 EUR 
     5,67 EUR
     ...

There is one whitespace before &#39;EUR&#39; and I ignore 0,XX EUR.

I tried: 

`grep &#39;[1-9][0-9]*,[0-9]\{2\}\sEUR&#39; =&gt; didn&#39;t match !`

`grep &#39;[1-9][0-9]*,[0-9]\{2\} EUR&#39; =&gt; worked !`

`grep &#39;[1-9][0-9]*,[0-9]\{2\}\s*EUR&#39; =&gt; worked !`

`grep &#39;[1-9][0-9]*,[0-9]\{2\}\s[E]UR&#39;  =&gt; worked !`

Can somebody explain me pls, why I can&#39;t use `\s` but `\s*` and `\s[E]` matched?

OS: Ubuntu 10.04, grep v2.5



grep regex whitespace behavior

I&#39;m trying to use GNU find to find only the directories that contain no other directories, but may or may not contain regular files. 

My best guess so far has been:

    find dir -type d $ -not -exec ls -dA &#39;;&#39; $

but this just gets me a long list of &quot;.&quot;

Thanks!

Use GNU find to show only the leaf directories

In my makefile, I would like to check for the existence of a library and give an informative error message. I created a conditional that should exit the make process when the file is not found:

     9: ifeq ($(${JSONLIBPATH}),)
    10:    JSONLIBPATH = ${ALTJSONLIBDIR}/${LIBJSON}
    11: endif
    12: ifeq ($(${JSONLIBPATH}),)
    13:    $(error JSON library is not found. Please install libjson before building)
    14: endif 

My makefile gets stuck on line 13:

    Makefile:13: *** commands commence before first target.  Stop.

After line 13, my makefile has its targets.

I tried putting this conditional block into a target (e.g. a target called `isJSONLibraryInstalled`) but this does not execute correctly.

How would I check for a file&#39;s existence and handle the error case, before processing targets? Apologies if this is a dumb question.

GNU make yields &quot;commands commence before first target&quot; error

Today I had to use the `basename()` function, and the `man 3 basename` ([here][1]) gave me some strange message:

&gt;**Notes**
&gt;
&gt;There are two different versions of *basename()* - the **POSIX** version described above, and the **GNU version**, which one gets after  
&gt;  
&gt;`#define _GNU_SOURCE`  
&gt;`#include &lt;string.h&gt; `

I&#39;m wondering what this `#define _GNU_SOURCE` means: is it *tainting* the code I write with a GNU-related license? Or is it simply used to tell the compiler something like &quot;*Well, I know, this set of functions is not POSIX, thus not portable, but I&#39;d like to use it anyway*&quot;.

If so, why not give people different headers, instead of having to define some obscure macro to get one function implementation or the other? 

Something also bugs me: how does the compiler know which function implementation to link with the executable? Does it use this `#define` as well?

Anybody have some pointers to give me?


  [1]: http://www.kernel.org/doc/man-pages/online/pages/man3/basename.3.html#NOTES

What does &quot;#define _GNU_SOURCE&quot; imply?

I am trying to force make file to display next string:

    &quot;Please execute next commands:
    setenv PATH /usr/local/greenhills/mips5/linux86:$PATH&quot;

The problem is with `&quot;$PATH&quot;`. Command

    @echo &quot;setenv PATH /usr/local/greenhills/mips5/linux86:$PATH&quot;

cause a result
    

    &quot;setenv PATH /usr/local/greenhills/mips5/linux86:ATH&quot;

any combinations of escape characters, quotes, `&quot;$(shell echo &quot;` didn&#39;t get required results...

Any suggestions? 

Make file echo displaying &quot;$PATH&quot; string

For various reasons, it would be convenient for me to specify .PHONY in multiple parts of a makefile. I feel like I&#39;m not correctly understanding how this works, but is this possible?

Instead of `.PHONY: clean cleanall`
do:

    .PHONY: clean
    &lt;some text&gt;
    .PHONY: cleanall

Is it possible to have multiple .PHONY targets in a GNU makefile?

I&#39;ve used rake a bit (a Ruby make program), and it has an option to get a list of all the available targets, eg

    &gt; rake --tasks
    rake db:charset      # retrieve the charset for your data...
    rake db:collation    # retrieve the collation for your da...
    rake db:create       # Creates the databases defined in y...
    rake db:drop         # Drops the database for your curren...
    ...

but there seems to be no option to do this in GNU make. 

Apparently the code is almost there for it, as of 2007 - http://www.mail-archive.com/help-make@gnu.org/msg06434.html. 

Anyway, I made little hack to extract the targets from a makefile, which you can include in a makefile. 

    list:
        @grep &#39;^[^#[:space:]].*:&#39; Makefile

It will give you a list of the defined targets. It&#39;s just a start - it doesn&#39;t filter out the dependencies, for instance. 

    &gt; make list
    list:
    copy:
    run:
    plot:
    turnin:



Content Type	Original Author	Original Content on Stackoverflow
Question	Justin	View Question on Stackoverflow
Solution 1 - Makefile	Beta	View Answer on Stackoverflow
Solution 2 - Makefile	Vlad	View Answer on Stackoverflow

How to get the invoking target of makefile?

Makefile Problem Overview

Makefile Solutions

Solution 1 - Makefile

Solution 2 - Makefile

Is there a tool to profile sqlite queries?

Why doesn't C++ have virtual variables?

Attributions