They control the behaviour of make for the tagged command lines:

* `@` suppresses the normal &#39;echo&#39; of the command that is executed.

* `-` means ignore the exit status of the command that is executed (normally, a non-zero exit status would stop that part of the build).

* `+` means &#39;execute this command under `make -n`&#39; (or &#39;make -t&#39; or &#39;make -q&#39;) when commands are not normally executed. See also the POSIX specification for [`make`](http://pubs.opengroup.org/onlinepubs/9699919799/utilities/make.html) and also [&#167;9.3](https://www.gnu.org/software/make/manual/html_node/Instead-of-Execution.html#Instead-of-Execution) of the GNU Make manual.

The `+` notation is a (POSIX-standardized) generalization of the _de facto_  (non-standardized) mechanism whereby a command line containing `${MAKE}` or `$(MAKE)` is executed under `make -n`.

(`@` is discussed in [&#167;5.2](https://www.gnu.org/software/make/manual/make.html#Recipe-Echoing) of the GNU Make manual; `-` is described in [&#167;5.5](https://www.gnu.org/software/make/manual/make.html#Errors-in-Recipes); and [&#167;5.7.1](https://www.gnu.org/software/make/manual/make.html#How-the-MAKE-Variable-Works) mentions the use of `+`.)


`@` prevents the command line from echoing out to the console. You can do it globally with `-s` or `--keep-silent`

`-` tells make to keep going, even if the command fails for some reason. You can do it globally via the `-i` flag (or `--ignore-errors`).

`+` I was not familar with before you asked. As near as I can tell, it negates the effect of `-n`, `-t`, and `-q`, all of which basically tell make to not actually run the commands. So a line with a `+` at the front would get run anyway.

If you read the official Gnu Make manual, they are all mentioned in [Chapter 5][1]. In my old copy of the manual that was the chapter on &quot;commands&quot;, but term du jour now seems to be &quot;recipes&quot;.


  [1]: http://www.gnu.org/software/make/manual/make.html#Recipes

Sorry for this basic question but my searches on this are not turning up anything other than how to get a dictionary&#39;s key based on its value which I would prefer not to use as I simply want the text/name of the key and am worried that searching by value may end up returning 2 or more keys if the dictionary has a lot of entries... what I am trying to do is this:

    mydictionary={&#39;keyname&#39;:&#39;somevalue&#39;}
    for current in mydictionary:

       result = mydictionary.(some_function_to_get_key_name)[current]
       print result
       &quot;keyname&quot;

The reason for this is that I am printing these out to a document and I want to use the key name and the value in doing this

I have seen the method below but this seems to just return the key&#39;s value

    get(key[, default])

How can I get dictionary key as variable directly in Python (not by searching from value)?

Is it possible, using Python, to merge separate PDF files?  

Assuming so, I need to extend this a little further.  I am hoping to loop through folders in a directory and repeat this procedure.  

And I may be pushing my luck, but is it possible to exclude a page that is contained in each of the PDFs (my report generation always creates an extra blank page).

Merge PDF files

In the GNU Makefile manual, it [mentions][1] these prefixes.

&gt; If .ONESHELL is provided, then only the first line of the recipe will be checked for the special prefix characters (‘@’, ‘-’, and ‘+’).

What do these prefixes do, and where are they mentioned?

  [1]: http://www.gnu.org/software/make/manual/make.html#One-Shell

What do @, - and + do as prefixes to recipe lines in Make?

In the GNU Makefile manual, it <a href="http://www.gnu.org/software/make/manual/make.html#One-Shell" target="_blank" rel="noopener noreferrer">mentions</a> these prefixes.
> If .ONESHELL is provided, then only the first line of the recipe will be checked for the special prefix characters (‘@’, ‘-’, and ‘+’).
What do these prefixes do, and where are they mentioned?

Lately at work, I&#39;ve been doing some translation from Makefiles to an alternative build system. I&#39;ve seen some pretty hairy Make code in some places using functional map, filter, and foreach constructs. This surprised me since I think build scripts ought to be as declarative as possible.

Anyway, this got me thinking: is the Makefile language (say the latest GNU make to be specific) Turing complete? 

Are makefiles Turing complete?

I think this is a question that has been asked many times but I cannot find the *right* way to do it.

I have the following structure:

    project/
    project/Makefile
    project/code
    project/code/*.cc
    project/code/Makefile

When I am in the directory &#39;project/code&#39; and call &quot;make project_code&quot; my code is compiling correctly.

I would like to do that when I am in &#39;project/&#39;, just calling &quot;make project_code&quot; as if I was in &#39;project/code&#39;.

The makefile &#39;project/Makefile&#39; will contain other rules (such as &#39;install&#39;) and some rules to compile as if I was in &#39;project/code&#39;. And for that, I am requesting your help... Thanks.



Subdirectories and Makefiles

I am trying to force make file to display next string:

    &quot;Please execute next commands:
    setenv PATH /usr/local/greenhills/mips5/linux86:$PATH&quot;

The problem is with `&quot;$PATH&quot;`. Command

    @echo &quot;setenv PATH /usr/local/greenhills/mips5/linux86:$PATH&quot;

cause a result
    

    &quot;setenv PATH /usr/local/greenhills/mips5/linux86:ATH&quot;

any combinations of escape characters, quotes, `&quot;$(shell echo &quot;` didn&#39;t get required results...

Any suggestions? 

Make file echo displaying &quot;$PATH&quot; string

I am doing a project which is growing pretty fast and keeping the object files up date is no option. The problem beyond wildcard command lies somewhere between &quot;I do not want recursive makefiles&quot; and &quot;I do not want it to list by hand&quot;. The objects are supposed to go into a separate directory, which works already.
Note: I am not _that_ used to makefiles, I know the basics, but everything beyond...

So my question: 
&lt;b&gt; How to scan a src folder recursively and do that in a smart manner?&lt;/b&gt;

I already did it with multiple SRC variables but that&#39;s ugly and clutters the whole makefile with an increasing number of directories.

What I currently use is:

    OS = Linux
    
    VERSION = 0.0.1
    CC      = /usr/bin/gcc
    CFLAGS  = -Wall -g -D_REENTRANT -DVERSION=\&quot;$(VERSION)\&quot;
    LDFLAGS = -lm `pkg-config --cflags gtk+-2.0` `pkg-config --libs gtk+-2.0`
    
    BUILDDIR = build
    SOURCEDIR = src
    HEADERDIR = src
    
    SOURCES = $(wildcard $(SOURCEDIR)/*.c)
    OBJECTS = $(patsubst $(SOURCEDIR)/%.c, $(BUILDDIR)/%.o, $(SOURCES))
    
    NAME = cinnamon
    BINARY = cinnamon.bin
    
    ECHO = echo
    RM = rm -rf
    MKDIR = mkdir
    INSTALL = install
    
    .PHONY: all clean setup
    
    all: $(BINARY)
    
    
    $(BINARY): $(BUILDDIR)/$(OBJECTS)
    	$(CC) $(CFLAGS) $(LDFLAGS) -I$(HEADERDIR) -I$(SOURCEDIR) $(OBJECTS) -o $(BINARY) 
    
    
    $(BUILDDIR)/%.o: $(SOURCEDIR)/%.c
    	$(CC) $(CFLAGS) $(LDFLAGS) -I$(HEADERDIR) -I$(SOURCEDIR) -c $&lt; -o $@
    
    setup:
    	$(MKDIR) -p $(BUILDDIR)
    
    install:
    	$(INSTALL) -m 755 -o 0 -g 0 -d $(DESTDIR)/usr/local/bin/
    	$(INSTALL) -m 755 -o 0 -g 0 $(BINARY) $(DESTDIR)/usr/local/bin/$(BINARY)
    	$(INSTALL) -m 755 -o 0 -g 0 -d $(DESTDIR)/usr/local/$(NAME)/ui/
    	$(INSTALL) -m 644 -o 0 -g 0 ./ui/*.ui $(DESTDIR)/usr/local/$(NAME)/ui/
    #	$(INSTALL) -m 755 -o 0 -g 0 -d $(DESTDIR)/usr/local/$(NAME)/model/
    #	$(INSTALL) -m 644 -o 0 -g 0 ./model/*.model $(DESTDIR)/usr/local/$(NAME)/model/
    
    clean:
    	$(RM) $(BINARY) $(OBJECTS)
    
    distclean: clean
    
    
    help:
    	@$(ECHO) &quot;Targets:&quot;
    	@$(ECHO) &quot;all     - buildcompile what is necessary&quot;
    	@$(ECHO) &quot;clean   - cleanup old .o and .bin&quot;
    	@$(ECHO) &quot;install - not yet fully supported&quot;


Thanks to answer #1 it boils down to how to solve this:

    $(BUILDDIR)/%.o: $(SOURCEDIR)/%.c
    	$(CC) $(CFLAGS) $(LDFLAGS) $(SOURCETREE) -c $&lt; -o $@

especially in the case of BUILDDIR = build and SOURCEDIR having to be replaced with the single .c files from SOURCES including their paths :/

Makefile issue: smart way to scan directory tree for .c files

Make seems to me simply a shell script with slightly easier handling of command line arguments.

Why is it standard to run make instead of ./make.sh

Why use make over a shell script?

I want to disable builtin rules and variables as per passing the [`-r` and `-R` options][1] to GNU make, from inside the make file. Other solutions that allow me to do this implicitly and transparently are also welcome.

I&#39;ve found [several references][2] to using [`MAKEFLAGS`][3], and had similar problems.


  [1]: http://www.gnu.org/software/make/manual/make.html#Options-Summary
  [2]: http://blog.electric-cloud.com/2009/08/19/makefile-performance-built-in-rules/#comment-219
  [3]: http://www.gnu.org/software/make/manual/make.html#Quick-Reference

Disable make builtin rules and variables from inside the make file

For various reasons, it would be convenient for me to specify .PHONY in multiple parts of a makefile. I feel like I&#39;m not correctly understanding how this works, but is this possible?

Instead of `.PHONY: clean cleanall`
do:

    .PHONY: clean
    &lt;some text&gt;
    .PHONY: cleanall

Is it possible to have multiple .PHONY targets in a GNU makefile?

I&#39;ve used rake a bit (a Ruby make program), and it has an option to get a list of all the available targets, eg

    &gt; rake --tasks
    rake db:charset      # retrieve the charset for your data...
    rake db:collation    # retrieve the collation for your da...
    rake db:create       # Creates the databases defined in y...
    rake db:drop         # Drops the database for your curren...
    ...

but there seems to be no option to do this in GNU make. 

Apparently the code is almost there for it, as of 2007 - http://www.mail-archive.com/help-make@gnu.org/msg06434.html. 

Anyway, I made little hack to extract the targets from a makefile, which you can include in a makefile. 

    list:
        @grep &#39;^[^#[:space:]].*:&#39; Makefile

It will give you a list of the defined targets. It&#39;s just a start - it doesn&#39;t filter out the dependencies, for instance. 

    &gt; make list
    list:
    copy:
    run:
    plot:
    turnin:



How do you get the list of targets in a makefile?

I&#39;m working on a large C++ project built with CMake on Linux.  CMake runs okay, producing a horde of Makefiles in the tree of modules and applications. Running GNU `make` leads to linker errors.  How can I get `make` to print out the exact commands before running them?

The -d option does not print the commands, but plenty of information that hasn&#39;t been helpful.

The -n option prints all the commands, but does not run them, so I can&#39;t tell were exactly the trouble is. Examining the stdout from make -n, I don&#39;t see any commands that are relevant. I suspect some commands change depending on the results of earlier commands, and the hierarchy of Makefiles makes it difficult to tell what&#39;s really going on.

I don&#39;t see any other options in make&#39;s *man* page that seem helpful.



Content Type	Original Author	Original Content on Stackoverflow
Question	Matt Joiner	View Question on Stackoverflow
Solution 1 - Makefile	Jonathan Leffler	View Answer on Stackoverflow
Solution 2 - Makefile	T.E.D.	View Answer on Stackoverflow

What do @, - and + do as prefixes to recipe lines in Make?

Makefile Problem Overview

Makefile Solutions

Solution 1 - Makefile

Solution 2 - Makefile

Merge PDF files

How can I get dictionary key as variable directly in Python (not by searching from value)?

Attributions