From the [manual][1]: 

    $(error Bad svn version v1.4, please install v1.6)

This will result `make` to a fatal error:

    $ make
    Makefile:2: *** Bad svn version v1.4, please install v1.6.  Stop.

  [1]: http://www.gnu.org/software/automake/manual/make/Make-Control-Functions.html

While $(error... works, sometimes its easier to use a rule that fails

    test_svn_version:
            @if [ $$(svn --version --quiet | \
                    perl -ne &#39;@a=split(/\./); \
                              print $$a[0]*10000 + $$a[1]*100 + $$a[2]&#39;) \
                  -lt 10600 ]; \
            then \
                echo &gt;&amp;2 &quot;Svn version $$(svn --version --quiet) too old; upgrade to v1.6&quot;;
                false; \
            fi

Then you make test\_svn\_version a prerequisite of your top level target.

The conditional needs some attention too.
&lt;pre&gt;
ifeq ($(shell svnversion --version | sed s/[^0-9\.]*://), 1.4) 
    $(error Bad svnversion v1.4, please install v1.6)
endif 
&lt;/pre&gt;

Given a set of 100 different strings of equal length, how can you quantify the probability that a SHA1 digest collision for the strings is unlikely... ? 



Probability of SHA1 collisions

What is the most efficient/recommended way of comparing two NSDates?  I would like to be able to see if both dates are on the same day, irrespective of the time and have started writing some code that uses the timeIntervalSinceDate: method within the NSDate class and gets the integer of this value divided by the number of seconds in a day.  This seems long winded and I feel like I am missing something obvious.

The code I am trying to fix is:

    if (!([key compare:todaysDate] == NSOrderedDescending))
    {
        todaysDateSection = [eventSectionsArray count] - 1;
    }

where key and todaysDate are NSDate objects and todaysDate is creating using:

    NSDate *todaysDate = [[NSDate alloc] init];

Regards

Dave 

Comparing two NSDates and ignoring the time component

I want to detect a condition in my makefile where a tool is the wrong version and force the make to fail with an error message indicating the item is not the right version.

Can anyone give an example of doing this?

I tried the following but it is not the right syntax:

    ifeq &quot;$(shell svnversion --version | sed s/[^0-9\.]*://)&quot; &quot;1.4&quot;
    $error(&quot;Bad svnversion v1.4, please install v1.6&quot;)
    endif


Thanks.

How to force an error in a gnumake file

I want to detect a condition in my makefile where a tool is the wrong version and force the make to fail with an error message indicating the item is not the right version.
Can anyone give an example of doing this?
I tried the following but it is not the right syntax:
<pre><code class="hljs language-bash">ifeq "$(shell svnversion --version | sed s/[^0-9\.]*://)" "1.4"
$error("Bad svnversion v1.4, please install v1.6")
endif
</code></pre>
Thanks.

In my GNUmakefile, I would like to have a rule that uses a temporary directory.  For example:

    out.tar: TMP := $(shell mktemp -d)
            echo hi $(TMP)/hi.txt
            tar -C $(TMP) cf $@ .
            rm -rf $(TMP)

As written, the above rule creates the temporary directory at the time that the rule is *parsed*.  This means that, even I don&#39;t make out.tar all the time, many temporary directories get created.  I would like to avoid my /tmp being littered with unused temporary directories.

Is there a way to cause the variable to only be defined when the rule is fired, as opposed to whenever it is defined?

My main thought is to dump the mktemp and tar into a shell script but that seems somewhat unsightly.

Define make variable at rule execution time

Is it possible to perform some operations on variables in a makefile?
For instance, defining

    JPI=4
    JPJ=2

is it possible to define in the same makefile a variable `JPIJ` equal to the expanded value of `$(JPI)*$(JPJ)`?


How do I perform arithmetic in a makefile?

I want to create directories using makefile. My project directory is like this

    +--Project  
       +--output  
       +--source  
         +Testfile.cpp  
       +Makefile  

I want to put all the objects and output into the respective output folder. I want to create folder structure which would be like this after compiling.

    +--Project
       +--output
         +--debug (or release)
           +--objs
             +Testfile.o
           +Testfile (my executable file)
       +--source
         +Testfile.cpp
       +Makefile

I tried with several options, but could not succeed. Please help me to make directories using make file. I&#39;m posting my Makefile for your consideration.

        
    #---------------------------------------------------------------------
    # Input dirs, names, files
    #---------------------------------------------------------------------
    OUTPUT_ROOT := output/
    
    TITLE_NAME := TestProj 
    
    ifdef DEBUG 
    	TITLE_NAME += _DEBUG
    else
    ifdef RELEASE
    	TITLE_NAME += _RELEASE
    endif
    endif
    
    
    # Include all the source files here with the directory tree
    SOURCES := \
    		source/TestFile.cpp \
    
    #---------------------------------------------------------------------
    # configs
    #---------------------------------------------------------------------
    ifdef DEBUG
    OUT_DIR		:= $(OUTPUT_ROOT)debug
    CC_FLAGS	:= -c -Wall
    else
    ifdef RELEASE
    OUT_DIR		:= $(OUTPUT_ROOT)release
    CC_FLAGS	:= -c -Wall
    else
    $(error no build type defined)
    endif
    endif
    
    # Put objects in the output directory.
    OUT_O_DIR	:= $(OUT_DIR)/objs
    
    #---------------------------------------------------------------------
    # settings
    #---------------------------------------------------------------------
    OBJS = $(SOURCES:.cpp=.o)
    DIRS = $(subst /,/,$(sort $(dir $(OBJS))))
    DIR_TARGET = $(OUT_DIR)
    
    OUTPUT_TARGET = $(OUT_DIR)/$(TITLE_NAME)
    
    CC_FLAGS +=   
    
    LCF_FLAGS := 
    
    LD_FLAGS := 
    
    #---------------------------------------------------------------------
    # executables
    #---------------------------------------------------------------------
    MD := mkdir
    RM := rm
    CC := g++
    
    #---------------------------------------------------------------------
    # rules
    #---------------------------------------------------------------------
    .PHONY: all clean title 
    
    all: title 
    
    clean:
    	$(RM) -rf $(OUT_DIR)
    
    $(DIR_TARGET):
    	$(MD) -p $(DIRS)
    
    .cpp.o: 
    	@$(CC) -c $&lt; -o $@
    
    $(OBJS): $(OUT_O_DIR)/%.o: %.cpp
    	@$(CC) -c $&lt; -o $@
    
    title: $(DIR_TARGET) $(OBJS)

 


Create directories using make file

I need to execute some make rules conditionally, only if the Python installed is greater than a certain version (say 2.5).

I thought I could do something like executing:

    python -c &#39;import sys; print int(sys.version_info &gt;= (2,5))&#39;

and then using the output (&#39;1&#39; if ok, &#39;0&#39; otherwise) in a `ifeq` make statement.

In a simple bash shell script it&#39;s just:

    MY_VAR=`python -c &#39;import sys; print int(sys.version_info &gt;= (2,5))&#39;`

but that doesn&#39;t work in a Makefile.

Any suggestions? I could use any other sensible workaround to achieve this.

How to assign the output of a command to a Makefile variable

Most Linux apps are compiled with:

    make
    make install clean

As I understand it, the `make` command takes names of build targets as arguments. So for example `install` is usually a target that copies some files to standard locations, and `clean` is a target that removes temporary files.

But what target will `make` build if no arguments are specified (e.g. the first command in my example)?



How does &quot;make&quot; app know default target to build if no target is specified?

I am using a GNU-make Makefile to build a C project with several targets (`all`, `clean`, and a few project specific targets). In the process of debugging, I would like to append some flags to a single build without permanently editing the Makefile (e.g. add debugging symbols or set a preprocessor flag).

In the past, I have done that as follows (using the debugging symbols example):

    make target CFLAGS+=-g

Unfortunately, this is not appending to the `CFLAGS` variable, but instead, clearing it and stopping it from compiling. Is there a clean way of doing this without defining some sort of dummy variable appended to the end of `CFLAGS` and `LDFLAGS`?

Append to GNU make variables via command line

After years of not using make, I find myself needing it again, the gnu version now.  I&#39;m pretty sure I should be able to do what I want, but haven&#39;t figured out how, or found an answer with Google, etc.

I&#39;m trying to create a test target which will execute my program a number of times, saving the results in a log file.  Some tests should cause my program to abort.  Unfortunately, my makefile aborts on the first test which leads to an error.  I have something like:

    # Makefile
    # 
    test:
            myProg -h &gt; test.log              # Display help
            myProg good_input &gt;&gt; test.log     # should run fine
            myProg bad_input1 &gt;&gt; test.log      # Error 1
            myProg bad_input2 &gt;&gt; test.log      # Error 2

With the above, make quits after the bad_input1 run, never getting to the bad_input2 run.






How to have GNU make explicitly test for failure?

I&#39;m getting some unexpected results calling one makefile from another.  I have two makefiles, one called `/path/to/project/makefile` and one called `/path/to/project/gtest-1.4.0/make/Makefile`.  I&#39;m attempting to have the former call the latter.  In /path/to/project/makefile, I have

    dev: $(OBJ_FILES)
      $(CPPC) $(LIBS) $(FLAGS_DEV) $(OBJ_FILES) -o $(BIN_DIR)/$(PROJECT)
      $(MAKE) -f ./gtest-1.4.0/make/Makefile

    clean:
      rm -f ./*~ ./gmon.out ./core $(SRC_DIR)/*~ $(OBJ_DIR)/*.o
      rm -f ../svn-commit.tmp~
      rm -f $(BIN_DIR)/$(PROJECT)
      make -f gtest-1.4.0/make/Makefile clean

And in `/path/to/project/gtest-1.4.0/make/Makefile` I have

    all: $(TESTS)

    clean:
      rm -f $(TESTS) gtest.a gtest_main.a *.o

Issuing the following:

    cd /path/to/project
    make

Outputs:

    make -f ./gtest-1.4.0/make/Makefile
    make[1]: Entering directory `/path/to/project&#39;
    make[1]: Nothing to be done for `all&#39;.
    make[1]: Leaving directory `/path/to/project&#39;

However, when I issue these commands:

    cd /path/to/project
    make clean

I see:

    make -f gtest-1.4.0/make/Makefile clean
    make[1]: Entering directory `/path/to/project&#39;
    rm -f  gtest.a gtest_main.a *.o
    make[1]: Leaving directory `/path/to/project&#39;

I don&#39;t understand: In both cases, `/path/to/project/makefile` is telling me it&#39;s entering the current working directory.  In the first case, it doesn&#39;t think it has work to do (when it does) and in the second case, it&#39;s able to find the appropriate directive (when the output is telling me it&#39;s looking in the wrong directory) yet it tries to run the `rm` command in `/path/to/project`, instead of `/path/to/makefile/gtest-1.4.0/make/`.

Am I missing something fundamental to calling makefiles from one another?  Have I made an egregious conceptual mistake, or hit a common pitfall?  How do I effectively change directories and call a second makefile from within the first?  My understanding was that simply calling `make -f &lt;name&gt;` would be enough.

This is make/gmake 3.81 in bash.

How to call Makefile from another Makefile?

It&#39;s been a while since I&#39;ve used `make`, so bear with me...

I&#39;ve got a directory, `flac`, containing .FLAC files. I&#39;ve got a corresponding directory, `mp3` containing MP3 files. If a FLAC file is newer than the corresponding MP3 file (or the corresponding MP3 file doesn&#39;t exist), then I want to run a bunch of commands to convert the FLAC file to an MP3 file, and copy the tags across.

The kicker: I need to search the `flac` directory recursively, and create corresponding subdirectories in the `mp3` directory. The directories and files can have spaces in the names, and are named in UTF-8.

And I want to use `make` to drive this.


Content Type	Original Author	Original Content on Stackoverflow
Question	WilliamKF	View Question on Stackoverflow
Solution 1 - Makefile	LiraNuna	View Answer on Stackoverflow
Solution 2 - Makefile	Chris Dodd	View Answer on Stackoverflow
Solution 3 - Makefile	Beta	View Answer on Stackoverflow

How to force an error in a gnumake file

Makefile Problem Overview

Makefile Solutions

Solution 1 - Makefile

Solution 2 - Makefile

Solution 3 - Makefile

Comparing two NSDates and ignoring the time component

Probability of SHA1 collisions

Attributions