How do I properly escape data for a Makefile?

I'm dynamically generating config.mk with a bash script which will be used by a Makefile. The file is constructed with:

cat > config.mk <<CFG
SOMEVAR := $value_from_bash1
ANOTHER := $value_from_bash2
CFG

How do I ensure that the generated file really contains the contents of $value_from_bash*, and not something expanded / interpreted? I probably need to escape $ to $$ and \ to \\, but are there other characters that needs to be escaped? Perhaps there is a special literal assignment I've not heard of?

Spaces seems to be troublesome too:

$ ls -1
a b
a
$ cat Makefile
f := a b
default_target:
    echo "$(firstword $(wildcard ${f}))"
$ make
a

If I use f := a\ b it works (using quotes like f := 'a b' did not work either, makefile just treats it as a regular character)

Okay, it turned out that Makefiles need little escaping for itself, but the commands which are executed by the shell interpreter need to be escaped.

Characters which have a special meaning in Makefile and that need to be escaped are:

• sharp (#, comment) becomes \#
• dollar ($, begin of variable) becomes $$

Newlines cannot be inserted in a variable, but to avoid breaking the rest of the Makefile, prepend it with a backslash so the line break will be ignored.

Too bad a backslash itself cannot be escaped (\\ will still be \\ and not \ as you might expect). This makes it not possible to put a literal slash on the end of a string as it will either eat the newline or the hash of a following comment. A space can be put on the end of the line, but that'll also be put in the variable itself.

The recipe itself is interpreted as a shell command, without any fancy escaping, so you've to escape data yourself, just imagine that you're writing a shellscript and inserting the variables from other files. The strategy here would be putting the variables between single quotes and escape only ' with '\'' (close the string, insert a literal ' and start a new string). Example: mornin' all becomes 'morning'\'' all' which is equivalent to "morning' all".

The firstword+wildcard issue is caused by the fact that filenames with spaces in them are treated as separate filenames by firstword. Furthermore, wildcard expands escapes using \ so x\ y is matches as one word, x y and not two words.

It seems that the full answer to this question is found nowhere on the internet, so I finally sat down and figured it out for the Windows case.

Specifically, the "Windows case" refers to file names that are valid in Windows, meaning that they do not contain the characters \, /, *, ?, ", ^, <, >, |, or line breaks. It also means \ and / are both considered valid directory separators for the purposes of Make.

An example will clear it up better than I can explain. Basically, if you are trying to match this file path:

Child\a$b  {'}(a.o#$@,&+=~`),[].c

Then you have to write these rules:

all: Child\\a$$b\\\ \\\ {'}(a.o\#$$@,&+=~`),[].o

%.o: %.c
	$(CC) '$(subst ','"'"',$(subst \,,$(subst \\,/,$+)))'

Stare at it for a long time and it'll sort of start making some remote sense.

This works in my MSYS2 environment, so I presume it is correct.

1. I don't see how that makefile can work as you say. A pattern rule cannot be the default.
2. You're missing a $ in $(wildcard ...), so I think you haven't posted what you're really testing.
3. You should escape newlines too.