Subdirectories and Makefiles

I think this is a question that has been asked many times but I cannot find the right way to do it.

I have the following structure:

project/
project/Makefile
project/code
project/code/*.cc
project/code/Makefile

When I am in the directory 'project/code' and call "make project_code" my code is compiling correctly.

I would like to do that when I am in 'project/', just calling "make project_code" as if I was in 'project/code'.

The makefile 'project/Makefile' will contain other rules (such as 'install') and some rules to compile as if I was in 'project/code'. And for that, I am requesting your help... Thanks.

The simplest way is to do:

CODE_DIR = code

.PHONY: project_code

project_code:
       $(MAKE) -C $(CODE_DIR)

The .PHONY rule means that project_code is not a file that needs to be built, and the -C flag indicates a change in directory (equivalent to running cd code before calling make). You can use the same approach for calling other targets in the code Makefile.

For example:

clean:
       $(MAKE) -C $(CODE_DIR) clean

Try putting this rule in project/Makefile something like this (for GNU make):

.PHONY: project_code
project_code:
cd code && make