I have Windows 8.1 pro with an AMD processor. I installed the Android SDK and Eclipse. It works but the problem is that when I Create AVD and launch it shows this error:

   

&gt;  emulator: ERROR: x86 emulation currently requires hardware acceleration!  
&gt;  Please ensure Intel HAXM is properly installed and usable.  
&gt;  CPU acceleration status: HAX kernel module is not installed!

I have already installed Intel Hardware_Accelerated_Execution_Manager and I have enabled Virtual modulation from the boot menu, but it&#39;s still not working.

Error in launching AVD with AMD processor

I tried to install my app into Android L Preview Intel Atom Virtual Device, it failed with error:

**INSTALL_FAILED_NO_MATCHING_ABIS**

What does it mean?

INSTALL_FAILED_NO_MATCHING_ABIS when install apk

I&#39;ve been racking my brain for a week trying to complete this assignment and I&#39;m hoping someone here can lead me toward the right path. Let me start with the instructor&#39;s instructions:


&gt; Your assignment is the opposite of our first lab assignment, which was to optimize a prime number program. Your purpose in this assignment is to pessimize the program, i.e. make it run slower. Both of these are CPU-intensive programs. They take a few seconds to run on our lab PCs. You may not change the algorithm.
&gt;
&gt; To deoptimize the program, use your knowledge of how the Intel i7 pipeline operates. Imagine ways to re-order instruction paths to introduce WAR, RAW, and other hazards. Think of ways to minimize the effectiveness of the cache. Be diabolically incompetent.

The assignment gave a choice of Whetstone or Monte-Carlo programs.  The cache-effectiveness comments are mostly only applicable to Whetstone, but I chose the Monte-Carlo simulation program:

    // Un-modified baseline for pessimization, as given in the assignment
    #include &lt;algorithm&gt;    // Needed for the &quot;max&quot; function
    #include &lt;cmath&gt;
    #include &lt;iostream&gt;
    
    // A simple implementation of the Box-Muller algorithm, used to generate
    // gaussian random numbers - necessary for the Monte Carlo method below
    // Note that C++11 actually provides std::normal_distribution&lt;&gt; in 
    // the &lt;random&gt; library, which can be used instead of this function
    double gaussian_box_muller() {
      double x = 0.0;
      double y = 0.0;
      double euclid_sq = 0.0;
    
      // Continue generating two uniform random variables
      // until the square of their &quot;euclidean distance&quot; 
      // is less than unity
      do {
        x = 2.0 * rand() / static_cast&lt;double&gt;(RAND_MAX)-1;
        y = 2.0 * rand() / static_cast&lt;double&gt;(RAND_MAX)-1;
        euclid_sq = x*x + y*y;
      } while (euclid_sq &gt;= 1.0);
    
      return x*sqrt(-2*log(euclid_sq)/euclid_sq);
    }
    
    // Pricing a European vanilla call option with a Monte Carlo method
    double monte_carlo_call_price(const int&amp; num_sims, const double&amp; S, const double&amp; K, const double&amp; r, const double&amp; v, const double&amp; T) {
      double S_adjust = S * exp(T*(r-0.5*v*v));
      double S_cur = 0.0;
      double payoff_sum = 0.0;
    
      for (int i=0; i&lt;num_sims; i++) {
        double gauss_bm = gaussian_box_muller();
        S_cur = S_adjust * exp(sqrt(v*v*T)*gauss_bm);
        payoff_sum += std::max(S_cur - K, 0.0);
      }
    
      return (payoff_sum / static_cast&lt;double&gt;(num_sims)) * exp(-r*T);
    }
    
    // Pricing a European vanilla put option with a Monte Carlo method
    double monte_carlo_put_price(const int&amp; num_sims, const double&amp; S, const double&amp; K, const double&amp; r, const double&amp; v, const double&amp; T) {
      double S_adjust = S * exp(T*(r-0.5*v*v));
      double S_cur = 0.0;
      double payoff_sum = 0.0;
    
      for (int i=0; i&lt;num_sims; i++) {
        double gauss_bm = gaussian_box_muller();
        S_cur = S_adjust * exp(sqrt(v*v*T)*gauss_bm);
        payoff_sum += std::max(K - S_cur, 0.0);
      }
    
      return (payoff_sum / static_cast&lt;double&gt;(num_sims)) * exp(-r*T);
    }
    
    int main(int argc, char **argv) {
      // First we create the parameter list                                                                               
      int num_sims = 10000000;   // Number of simulated asset paths                                                       
      double S = 100.0;  // Option price                                                                                  
      double K = 100.0;  // Strike price                                                                                  
      double r = 0.05;   // Risk-free rate (5%)                                                                           
      double v = 0.2;    // Volatility of the underlying (20%)                                                            
      double T = 1.0;    // One year until expiry                                                                         
    
      // Then we calculate the call/put values via Monte Carlo                                                                          
      double call = monte_carlo_call_price(num_sims, S, K, r, v, T);
      double put = monte_carlo_put_price(num_sims, S, K, r, v, T);
    
      // Finally we output the parameters and prices                                                                      
      std::cout &lt;&lt; &quot;Number of Paths: &quot; &lt;&lt; num_sims &lt;&lt; std::endl;
      std::cout &lt;&lt; &quot;Underlying:      &quot; &lt;&lt; S &lt;&lt; std::endl;
      std::cout &lt;&lt; &quot;Strike:          &quot; &lt;&lt; K &lt;&lt; std::endl;
      std::cout &lt;&lt; &quot;Risk-Free Rate:  &quot; &lt;&lt; r &lt;&lt; std::endl;
      std::cout &lt;&lt; &quot;Volatility:      &quot; &lt;&lt; v &lt;&lt; std::endl;
      std::cout &lt;&lt; &quot;Maturity:        &quot; &lt;&lt; T &lt;&lt; std::endl;
    
      std::cout &lt;&lt; &quot;Call Price:      &quot; &lt;&lt; call &lt;&lt; std::endl;
      std::cout &lt;&lt; &quot;Put Price:       &quot; &lt;&lt; put &lt;&lt; std::endl;
    
      return 0;
    }

The changes I have made seemed to increase the code running time by a second but I&#39;m not entirely sure what I can change to stall the pipeline without adding code. A point to the right direction would be awesome, I appreciate any responses.

---

## Update: [the professor who gave this assignment posted some details][1]

The highlights are:

* It&#39;s a second semester architecture class at a community college (using the Hennessy and Patterson textbook).
* the lab computers have Haswell CPUs
* The students have been exposed to the `CPUID` instruction and how to determine cache size, as well as intrinsics and the `CLFLUSH` instruction.
* any compiler options are allowed, and so is inline asm.
* Writing your own square root algorithm was announced as being outside the pale

Cowmoogun&#39;s comments on the meta thread indicate that [it wasn&#39;t clear compiler optimizations could be part of this, and assumed `-O0`][2], and that a 17% increase in run-time was reasonable.

So it sounds like the goal of the assignment was to get students to re-order the existing work to reduce instruction-level parallelism or things like that, but it&#39;s not a bad thing that people have delved deeper and learned more.

----

Keep in mind that this is a computer-architecture question, not a question about how to make C++ slow in general.


  [1]: https://meta.stackoverflow.com/a/323690/224132
  [2]: https://meta.stackoverflow.com/questions/323603/is-it-possible-for-some-too-broad-questions-to-be-exceptions-to-the-rule/323690#comment347466_323612

Deoptimizing a program for the pipeline in Intel Sandybridge-family CPUs

Lately Google and Intel have published a new way to run the emulator, which should work much better than the previous version (which has emulated ARM CPU). Here are some links about it: [this][1] and [this][2].

However, after installing the new components and creating a new emulator configuration as instructed, I get an error and I also can&#39;t see any improvements. I&#39;ve tried both API 10 and API 15, and with GPU enabled and disabled. None of those configurations helped. I&#39;ve also tried it on two different computers and didn&#39;t get any boost (and got the same errors).

It seems that on the posts I&#39;ve read about it, nobody had any problems with it and all report a much faster emulator.

The error it shows is:

    emulator: Failed to open the HAX device!
    HAX is not working and emulator runs in emulation mode
    emulator: Open HAX device failed

Why is it happening, and is there a way to fix it? Is there anyone else who gets those errors or vice versa?

By the way, I have an Intel CPU, if that could be a problem.

----

EDIT: 

here&#39;s what I see in the BIOS, so it should be available... :

![enter image description here][3]


  [1]: http://www.androidcentral.com/intel-releases-x86-system-image-android-emulator
  [2]: http://www.engadget.com/2012/05/24/intel-posts-x86-friendly-android-4-0-image/
  [3]: http://i.stack.imgur.com/LA6b0.jpg

Running the new Intel emulator for Android

I tried to run my Hello World application in Android Studio. I got the following error:

&gt; Emulator: ERROR: x86 emulation currently requires hardware
&gt; acceleration!
&gt;
&gt;Please ensure Intel HAXM is properly installed and usable.
&gt;
&gt;CPU acceleration status: HAX kernel module is not installed!

Can you tell me what I can do with the error?

Emulator: ERROR: x86 emulation currently requires hardware acceleration

I installed Android Studio and I had no problems with that. However, when I tried to run the emulator, it said that Intel HAXM was not installed.

So I found the installer, ran it, and it even though it said my laptop supports it, that it was not enabled. I went, enabled the Intel Virtualization Technology (VT-x), but I still got the same message.

I hear something about Hyper-V needs to be disabled, but when I go to _Turn Windows features on/off_, I cannot find it on that list.

Can someone help me with this?

I can&#39;t install intel HAXM

I&#39;m trying to use the Intel HAX x86 emulator for Windows (8, if that matters).  I installed everything and created an AVD for the android version, and everything appears correct, but when I run it, I get this output:

    Starting emulator for AVD &#39;x86_QVGA_Level10&#39;
    emulator: device fd:1044
    HAX is working and emulator runs in fast virt mode
    emulator: Failed to sync vcpu reg
    emulator: Failed to sync HAX vcpu context

and the emulator won&#39;t run.  The significant part of this error `(Failed to sync vcpu reg)` is not mentioned ANYWHERE online, except in the [source code for the HAX itself](http://mirror.yongbok.net/pub/linux/android/repository/external/qemu/target-i386/hax-all.c), but I can&#39;t figure out how to make any sense of this.

Can anyone advise about how to get past this error?  I really need to get this working, because debugging on device and in the default emulators is painfully slow.

How do I fix &quot;Failed to sync vcpu reg&quot; error?

I have an issue with my HAXM installation. Here is the thing. I got this error every single time I tried to install HAXM for my computer:
![Installation error print-screen][1]

Problem is, that my computer supports Virtualization Technology (see pic below). Any idea how to fix this issue?
![enter image description here][2]


  [1]: http://i.stack.imgur.com/IRJU3.png
  [2]: http://i.stack.imgur.com/yW2H5.png

Intel HAXM installation error - This computer does not support Intel Virtualization Technology (VT-x)

For the Intel architectures, is there a way to instruct the GCC compiler to generate code that always forces branch prediction a particular way in my code?  Does the Intel hardware even support this?  What about other compilers or hardwares?

I would use this in C++ code where I know the case I wish to run fast and do not care about the slow down when the other branch needs to be taken even when it has recently taken that branch.

    for (;;) {
      if (normal) { // How to tell compiler to always branch predict true value?
        doSomethingNormal();
      } else {
        exceptionalCase();
      }
    }

-----------------

As a follow on question for Evdzhan Mustafa, can the hint just specify a hint for the first time the processor encounters the instruction, all subsequent branch prediction, functioning normally?

Is there a compiler hint for GCC to force branch prediction to always go a certain way?

Starting with Pentium Pro (P6 microarchitecture), Intel redesigned it&#39;s microprocessors and used internal RISC core under the old CISC instructions. Since Pentium Pro all CISC instructions are divided into smaller parts (uops) and then executed by the RISC core. 

At the beginning it was clear for me that Intel decided to hide new internal architecture and force programmers to use &quot;CISC shell&quot;. Thanks to this decision Intel could fully redesign microprocessors architecture without breaking compatibility, it&#39;s reasonable.

However I don&#39;t understand one thing, why Intel still keeps an internal RISC instructions set hidden for so many years? Why wouldn&#39;t they let programmers use RISC instructions like the use old x86 CISC instructions set? 

If Intel keeps backward compatibility for so long (we still have virtual 8086 mode next to 64 bit mode), Why don&#39;t they allow us compile programs so they will bypass CISC instructions and use RISC core directly? This will open natural way to slowly abandon x86 instructions set, which is deprecated nowadays (this is the main reason why Intel decided to use RISC core inside, right?).

Looking at new Intel &#39;Core i&#39; series I see, that they only extends CISC instructions set adding AVX, SSE4 and others.

Why does Intel hide internal RISC core in their processors?

This question continues on my question here (on the advice of Mystical):

https://stackoverflow.com/questions/9992054/c-code-loop-performance

----------------

Continuing on my question, when i use packed instructions instead of scalar instructions the code using intrinsics would look very similar:

    for(int i=0; i&lt;size; i+=16) {
        y1 = _mm_load_ps(output[i]);
        …
        y4 = _mm_load_ps(output[i+12]);

        for(k=0; k&lt;ksize; k++){
            for(l=0; l&lt;ksize; l++){
                w  = _mm_set_ps1(weight[i+k+l]);

                x1 = _mm_load_ps(input[i+k+l]);
                y1 = _mm_add_ps(y1,_mm_mul_ps(w,x1));
                …
                x4 = _mm_load_ps(input[i+k+l+12]);
                y4 = _mm_add_ps(y4,_mm_mul_ps(w,x4));
            }
        }
        _mm_store_ps(&amp;output[i],y1);
        …
        _mm_store_ps(&amp;output[i+12],y4);
        }

The measured performance of this kernel is about 5.6 FP operations per cycle, although i would expect it to be exactly 4x the performance of the scalar version, i.e. 4.1,6=6,4 FP ops per cycle. 

Taking the move of the weight factor into account (thanks for pointing that out), the schedule looks like:

![schedule][1]

It looks like the schedule doesn&#39;t change, although there is an extra instruction after the `movss` operation that moves the scalar weight value to the XMM register and then uses `shufps` to copy this scalar value in the entire vector. It seems like the weight vector is ready to be used for the `mulps` in time taking the switching latency from load to the floating point domain into account, so this shouldn&#39;t incur any extra latency.

The `movaps` (aligned, packed move),`addps` &amp; `mulps` instructions that are used in this kernel (checked with assembly code) have the same latency &amp; throughput as their scalar versions, so this shouldn&#39;t incur any extra latency either.

Does anybody have an idea where this extra cycle per 8 cycles is spent on, assuming the maximum performance this kernel can get is 6.4 FP ops per cycle and it is running at 5.6 FP ops per cycle?


-------

By the way here is what the actual assembly looks like:

    …
    Block x: 
      movapsx  (%rax,%rcx,4), %xmm0
      movapsx  0x10(%rax,%rcx,4), %xmm1
      movapsx  0x20(%rax,%rcx,4), %xmm2
      movapsx  0x30(%rax,%rcx,4), %xmm3
      movssl  (%rdx,%rcx,4), %xmm4
      inc %rcx
      shufps $0x0, %xmm4, %xmm4               {fill weight vector}
      cmp $0x32, %rcx 
      mulps %xmm4, %xmm0 
      mulps %xmm4, %xmm1
      mulps %xmm4, %xmm2 
      mulps %xmm3, %xmm4
      addps %xmm0, %xmm5 
      addps %xmm1, %xmm6 
      addps %xmm2, %xmm7 
      addps %xmm4, %xmm8 
      jl 0x401ad6 &lt;Block x&gt; 
    …




  [1]: http://i.stack.imgur.com/vhKri.png

C code loop performance [continued]

LOOP ([Intel ref manual entry][1])
decrements ecx / rcx, [and then jumps if non-zero][2].  It&#39;s slow, but couldn&#39;t Intel have cheaply made it fast?  `dec/jnz` already [macro-fuses into a single uop][3] on Sandybridge-family; the only difference being that that sets flags.

`loop` on various microarchitectures, from [Agner Fog&#39;s instruction tables][4]:

* K8/K10: 7 m-ops
* **Bulldozer-family/Ryzen**: 1 m-op (same cost as macro-fused test-and-branch, or `jecxz`)

* P4: 4 uops (same as `jecxz`)
* P6 (PII/PIII): 8 uops
* Pentium M, Core2: 11 uops
* Nehalem: 6 uops.  (11 for `loope` / `loopne`).  Throughput = 4c (`loop`) or 7c (`loope/ne`).
* **SnB-family**: 7 uops.  (11 for `loope` / `loopne`).  **Throughput = one per 5 cycles**, as much of a bottleneck as keeping your loop counter in memory! `jecxz` is only 2 uops with same throughput as regular `jcc`
* Silvermont: 7 uops
* AMD Jaguar (low-power): 8 uops, 5c throughput
* Via Nano3000: 2 uops


---

Couldn&#39;t the decoders just decode the same as `lea rcx, [rcx-1]` / `jrcxz`?  That would be 3 uops.  At least that would be the case with no address-size prefix, otherwise it has to use `ecx` and truncate `RIP` to `EIP` if the jump is taken; **maybe the odd choice of address-size controlling the width of the decrement explains the many uops?**  (Fun fact: `rep`-string instructions have the same behaviour with using `ecx` with 32-bit address-size.)

Or better, just decode it as a fused dec-and-branch that doesn&#39;t set flags?  `dec ecx` / `jnz` on SnB decodes to a single uop (which does set flags).

I know that real code doesn&#39;t use it (because it&#39;s been slow since at least P5 or something), but AMD decided it was worth it to make it fast for Bulldozer.  Probably because it was easy.

---

* **Would it be easy for SnB-family uarch to have fast `loop`?**  If so, why don&#39;t they?  If not, why is it hard?  A lot of decoder transistors?  Or extra bits in a fused dec&amp;branch uop to record that it doesn&#39;t set flags?  What could those 7 uops be doing?  It&#39;s a really simple instruction.

* **What&#39;s special about Bulldozer that made a fast `loop` easy / worth it?**  Or did AMD waste a bunch of transistors on making `loop` fast?  If so, presumably someone thought it was a good idea.

----

**If `loop` was fast**, it would be perfect for [BigInteger arbitrary-precision `adc` loops, to avoid partial-flag stalls / slowdowns][5]  (see my comments on my answer), or any other case where you want to loop without touching flags.  It also has a minor code-size advantage over `dec/jnz`.  (And `dec/jnz` only macro-fuses on SnB-family).

On modern CPUs where `dec/jnz` is ok in an ADC loop, `loop` would still be nice for ADCX / ADOX loops (to preserve OF).

If `loop` had been fast, compilers would already be using it as a peephole optimization for code-size + speed on CPUs without macro-fusion.

---

It wouldn&#39;t stop me from getting annoyed at all the questions with bad 16bit code that uses `loop` for every loop, even when they also need another counter inside the loop.  But at least it wouldn&#39;t be *as* bad.


  [1]: http://felixcloutier.com/x86/LOOP:LOOPcc.html
  [2]: https://stackoverflow.com/questions/46881279/how-exactly-does-the-x86-loop-instruction-work/46881622#46881622
  [3]: https://stackoverflow.com/questions/31771526/x86-64-assembly-loop-conditions-and-out-of-order
  [4]: http://agner.org/optimize/
  [5]: https://stackoverflow.com/questions/32084204/problems-with-adc-sbb-and-inc-dec-in-tight-loops-on-some-cpus

Why is the loop instruction slow? Couldn&#39;t Intel have implemented it efficiently?

I tried installing Intel MPI Benchmark on my computer and I got this error:

    fork: retry: Resource temporarily unavailable

Then I received this error again when I ran `ls` and `top` command.

What is causing this error?

Configuration of my machine:

    Dell precision T7500
    Scientific Linux release 6.2 (Carbon)


fork: retry: Resource temporarily unavailable

From what I&#39;ve read it&#39;s used to fix bugs in the CPU without modifying the BIOS.
From my basic knowledge of Assembly I know that assembly instructions are split into microcodes internally by the CPU and executed accordingly. But intel somehow gives access to make some updates while the system is up and running.

Anyone has more info on them? Is there any documentation regarding what can it be done with microcodes and how can they be used?

------
EDIT: 
I&#39;ve read the wikipedia article: didn&#39;t figure out how can I write some on my own, and what uses it would have.

What is Intel microcode?

Double values store higher precision and are double the size of a float, but are Intel CPUs optimized for floats?

That is, are double operations just as fast or faster than float operations for +, -, *, and /?

Does the answer change for 64-bit architectures?


Is using double faster than float?

As [this question](https://stackoverflow.com/questions/199966/how-do-you-use-gcc-to-generate-assembly-code-in-intel-syntax) shows, with g++, I can do `g++ -S -masm=intel test.cpp`.
Also, with clang, I can do `clang++ -S test.cpp`, but `-masm=intel` is not supported by clang (`warning argument unused during compilation: -masm=intel`). How do I get intel syntax with clang?

How to generate assembly code with clang in Intel syntax?

I am trying to create a dumb version of a spin lock. Browsing the web, I came across a assembly instruction called &quot;PAUSE&quot; in x86 which is used to give hint to a processor that a spin-lock is currently running on this CPU. The intel manual and other information available state that 

&gt; The processor uses this hint to avoid the memory order violation in
&gt; most situations, which greatly improves processor performance. For
&gt; this reason, it is recommended that a PAUSE instruction be placed in
&gt; all spin-wait loops. The documentation also mentions that  &quot;wait(some
&gt; delay)&quot; is the pseudo implementation of the instruction.

The last line of the above paragraph is intuitive. If I am unsuccessful in grabbing the lock, I must wait for some time before grabbing the lock again.

However, what do we mean by memory order violation in case of a spin lock? 
Does &quot;memory order violation&quot; mean the incorrect *speculative* load/store of the instructions after spin-lock?

The spin-lock question has been asked on Stack overflow before but the memory order violation question remains unanswered (at-least for my understanding).

 

What is the purpose of the &quot;PAUSE&quot; instruction in x86?

I&#39;ve been trying to understand assembly language code generated by GCC and frequently encounter this instruction at the start of many functions including `_start()`, but couldn&#39;t find any guide explaining its purpose:
```
31-0000000000001040 &lt;_start&gt;:
32:    1040:	f3 0f 1e fa          	endbr64 
33-    1044:	31 ed                	xor    ebp,ebp

What does the endbr64 instruction actually do?

When talking about multi-threading, it often seems like threads are treated as equal - just the same as the main thread, but running next to it.

On some new processors, however, such as the [Apple &quot;M&quot; series][1] and the upcoming Intel [Alder Lake][2] series not all threads are equally as performant as these chips feature separate high-performance cores and high-efficiency, slower cores.

It’s not to say that there weren’t already things such as hyper-threading, but this seems to have a much larger performance implication.

Is there a way to query `std::thread`‘s properties and enforce on which cores they’ll run in C++?

  [1]: https://en.wikipedia.org/wiki/Apple_silicon#M_series
  [2]: https://en.wikipedia.org/wiki/Alder_Lake_(microprocessor)




How can I distinguish between high- and low-performance cores/threads in C++?

I&#39;m confused on how many flops per cycle per core can be done with Sandy-Bridge and Haswell.
As I understand it with SSE it should be 4 flops per cycle per core for SSE and 8 flops per cycle per core for AVX/AVX2.  

This seems to be verified here,
https://stackoverflow.com/questions/8389648/how-to-achieve-4-flops-per-cycle
,and here,
https://stackoverflow.com/questions/12027922/sandy-bridge-cpu-specification.

However the link below seems to indicate that Sandy-bridge can do 16 flops per cycle per core and Haswell 32 flops per cycle per core
http://www.extremetech.com/computing/136219-intels-haswell-is-an-unprecedented-threat-to-nvidia-amd.

Can someone explain this to me?

Edit:
I understand now why I was confused.  I thought the term FLOP only referred  to single floating point (SP).  I see now that the test at https://stackoverflow.com/questions/8389648/how-to-achieve-4-flops-per-cycle are actually on double floating point (DP) so they achieve 4 DP FLOPs/cycle for SSE and 8 DP FLOPs/cycle for AVX.  It would be interesting to redo these test on SP.

FLOPS per cycle for sandy-bridge and haswell SSE2/AVX/AVX2

A real question that I&#39;ve been asking myself lately is what design choices brought about x86 being a little endian architecture instead of a big endian architecture?

Why is x86 little endian?

I&#39;ve been trying to figure out a performance problem in an application and have finally narrowed it down to a really weird problem. The following piece of code runs 6 times slower on a Skylake CPU (i5-6500) if the `VZEROUPPER` instruction is commented out. I&#39;ve tested Sandy Bridge and Ivy Bridge CPUs and both versions run at the same speed, with or without `VZEROUPPER`.

Now I have a fairly good idea of what `VZEROUPPER` does and I think it should not matter at all to this code when there are no VEX coded instructions and no calls to any function which might contain them. The fact that it does not on other AVX capable CPUs appears to support this. So does table 11-2 in the [Intel&#174; 64 and IA-32 Architectures Optimization Reference Manual][1]

So what is going on? 

The only theory I have left is that there&#39;s a bug in the CPU and it&#39;s incorrectly triggering the &quot;save the upper half of the AVX registers&quot; procedure where it shouldn&#39;t. Or something else just as strange.

This is main.cpp:

&lt;!-- language: c --&gt;

    #include &lt;immintrin.h&gt;

    int slow_function( double i_a, double i_b, double i_c );

    int main()
    {
        /* DAZ and FTZ, does not change anything here. */
        _mm_setcsr( _mm_getcsr() | 0x8040 );

        /* This instruction fixes performance. */
        __asm__ __volatile__ ( &quot;vzeroupper&quot; : : : );

        int r = 0;
        for( unsigned j = 0; j &lt; 100000000; ++j )
        {
            r |= slow_function( 
                    0.84445079384884236262,
                    -6.1000481519580951328,
                    5.0302160279288017364 );
        }
        return r;
    }

and this is slow_function.cpp:

&lt;!-- language: c --&gt;

    #include &lt;immintrin.h&gt;

    int slow_function( double i_a, double i_b, double i_c )
    {
        __m128d sign_bit = _mm_set_sd( -0.0 );
        __m128d q_a = _mm_set_sd( i_a );
        __m128d q_b = _mm_set_sd( i_b );
        __m128d q_c = _mm_set_sd( i_c );

        int vmask;
        const __m128d zero = _mm_setzero_pd();

        __m128d q_abc = _mm_add_sd( _mm_add_sd( q_a, q_b ), q_c );
        
        if( _mm_comigt_sd( q_c, zero ) &amp;&amp; _mm_comigt_sd( q_abc, zero )  )
        {
            return 7;
        }

        __m128d discr = _mm_sub_sd(
            _mm_mul_sd( q_b, q_b ),
            _mm_mul_sd( _mm_mul_sd( q_a, q_c ), _mm_set_sd( 4.0 ) ) );

        __m128d sqrt_discr = _mm_sqrt_sd( discr, discr );
        __m128d q = sqrt_discr;
        __m128d v = _mm_div_pd(
            _mm_shuffle_pd( q, q_c, _MM_SHUFFLE2( 0, 0 ) ),
            _mm_shuffle_pd( q_a, q, _MM_SHUFFLE2( 0, 0 ) ) );
        vmask = _mm_movemask_pd(
            _mm_and_pd(
                _mm_cmplt_pd( zero, v ),
                _mm_cmple_pd( v, _mm_set1_pd( 1.0 ) ) ) );
        
        return vmask + 1;
    }

The function compiles down to this with clang:

     0:   f3 0f 7e e2             movq   %xmm2,%xmm4
     4:   66 0f 57 db             xorpd  %xmm3,%xmm3
     8:   66 0f 2f e3             comisd %xmm3,%xmm4
     c:   76 17                   jbe    25 &lt;_Z13slow_functionddd+0x25&gt;
     e:   66 0f 28 e9             movapd %xmm1,%xmm5
    12:   f2 0f 58 e8             addsd  %xmm0,%xmm5
    16:   f2 0f 58 ea             addsd  %xmm2,%xmm5
    1a:   66 0f 2f eb             comisd %xmm3,%xmm5
    1e:   b8 07 00 00 00          mov    $0x7,%eax
    23:   77 48                   ja     6d &lt;_Z13slow_functionddd+0x6d&gt;
    25:   f2 0f 59 c9             mulsd  %xmm1,%xmm1
    29:   66 0f 28 e8             movapd %xmm0,%xmm5
    2d:   f2 0f 59 2d 00 00 00    mulsd  0x0(%rip),%xmm5        # 35 &lt;_Z13slow_functionddd+0x35&gt;
    34:   00 
    35:   f2 0f 59 ea             mulsd  %xmm2,%xmm5
    39:   f2 0f 58 e9             addsd  %xmm1,%xmm5
    3d:   f3 0f 7e cd             movq   %xmm5,%xmm1
    41:   f2 0f 51 c9             sqrtsd %xmm1,%xmm1
    45:   f3 0f 7e c9             movq   %xmm1,%xmm1
    49:   66 0f 14 c1             unpcklpd %xmm1,%xmm0
    4d:   66 0f 14 cc             unpcklpd %xmm4,%xmm1
    51:   66 0f 5e c8             divpd  %xmm0,%xmm1
    55:   66 0f c2 d9 01          cmpltpd %xmm1,%xmm3
    5a:   66 0f c2 0d 00 00 00    cmplepd 0x0(%rip),%xmm1        # 63 &lt;_Z13slow_functionddd+0x63&gt;
    61:   00 02 
    63:   66 0f 54 cb             andpd  %xmm3,%xmm1
    67:   66 0f 50 c1             movmskpd %xmm1,%eax
    6b:   ff c0                   inc    %eax
    6d:   c3                      retq   

The generated code is different with gcc but it shows the same problem. An older version of the intel compiler generates yet another variation of the function which shows the problem too but only if `main.cpp` is not built with the intel compiler as it inserts calls to initialize some of its own libraries which probably end up doing `VZEROUPPER` somewhere.

And of course, if the whole thing is built with AVX support so the intrinsics are turned into VEX coded instructions, there is no problem either.

I&#39;ve tried profiling the code with `perf` on linux and most of the runtime usually lands on 1-2 instructions but not always the same ones depending on which version of the code I profile (gcc, clang, intel). Shortening the function appears to make the performance difference gradually go away so it looks like several instructions are causing the problem.

EDIT: Here&#39;s a pure assembly version, for linux. Comments below.

        .text
        .p2align    4, 0x90
        .globl _start
    _start:

        #vmovaps %ymm0, %ymm1  # This makes SSE code crawl.
        #vzeroupper            # This makes it fast again.

        movl    $100000000, %ebp
        .p2align    4, 0x90
    .LBB0_1:
        xorpd   %xmm0, %xmm0
        xorpd   %xmm1, %xmm1
        xorpd   %xmm2, %xmm2

        movq    %xmm2, %xmm4
        xorpd   %xmm3, %xmm3
        movapd  %xmm1, %xmm5
        addsd   %xmm0, %xmm5
        addsd   %xmm2, %xmm5
        mulsd   %xmm1, %xmm1
        movapd  %xmm0, %xmm5
        mulsd   %xmm2, %xmm5
        addsd   %xmm1, %xmm5
        movq    %xmm5, %xmm1
        sqrtsd  %xmm1, %xmm1
        movq    %xmm1, %xmm1
        unpcklpd    %xmm1, %xmm0
        unpcklpd    %xmm4, %xmm1

        decl    %ebp
        jne    .LBB0_1

        mov $0x1, %eax
        int $0x80

Ok, so as suspected in comments, using VEX coded instructions causes the slowdown. Using `VZEROUPPER` clears it up. But that still does not explain why.

As I understand it, not using `VZEROUPPER` is supposed to involve a cost to transition to old SSE instructions but not a permanent slowdown of them. Especially not such a large one. Taking loop overhead into account, the ratio is at least 10x, perhaps more.

I have tried messing with the assembly a little and float instructions are just as bad as double ones. I could not pinpoint the problem to a single instruction either.


  [1]: http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf

Why is this SSE code 6 times slower without VZEROUPPER on Skylake?

I can understand how one can write a program that uses multiple processes or threads: fork() a new process and use IPC, or create multiple threads and use those sorts of communication mechanisms.

I also understand context switching. That is, with only once CPU, the operating system schedules time for each process (and there are tons of scheduling algorithms out there) and thereby we achieve running multiple processes simultaneously.

And now that we have multi-core processors (or multi-processor computers), we could have two processes running simultaneously on two separate cores.

My question is about the last scenario: how does the kernel control which core a process runs on? Which system calls (in Linux, or even Windows) schedule a process on a specific core?

The reason I&#39;m asking: I&#39;m working on a project for school where we are to explore a recent topic in computing - and I chose multi-core architectures. There seems to be a lot of material on how to program in that kind of environment (how to watch for deadlock or race conditions) but not much on controlling the individual cores themselves. I would love to be able to write a few demonstration programs and present some assembly instructions or C code to the effect of &quot;See, I am running an infinite loop on the 2nd core, look at the spike in CPU utilization for *that specific core*&quot;.

Any code examples? Or tutorials?

edit: For clarification - many people have said that this is the purpose of the OS, and that one should let the OS take care of this. I completely agree! But then what I&#39;m asking (or trying to get a feel for) is what the operating system actually does to do this. Not the scheduling algorithm, but more &quot;once a core is chosen, what instructions must be executed to have that core start fetching instructions?&quot;

How to control which core a process runs on?

I have a few questions regarding Cache memories used in Multicore CPUs or Multiprocessor systems. (Although not directly related to programming, it has many repercussions while one writes software for multicore processors/multiprocessors systems, hence asking here!)

  1. In a multiprocessor system or a multicore processor (Intel Quad Core, Core two Duo etc..) does each cpu core/processor have its own cache memory (data and program cache)?

  2. Can one processor/core access each other&#39;s cache memory, because if they are allowed to access each other&#39;s cache, then I believe there might be lesser cache misses, in the scenario that if that particular processors cache does not have some data but some other second processors&#39; cache might have it thus avoiding a read from memory into cache of first processor? Is this assumption valid and true?

  3. Will there be any problems in allowing any processor to access other processor&#39;s cache memory?


How are cache memories shared in multicore Intel CPUs?

Just read this [fascinating article][1] about the 20x-200x slowdowns you can get on Intel CPUs with denormalized floats (floating point numbers very close to 0).

There is an option with SSE to round these off to 0, restoring performance when such floating point values are encountered. 

How do C# apps handle this? Is there an option to enable/disable `_MM_FLUSH_ZERO`?


  [1]: https://stackoverflow.com/a/9314926/1294758

How are denormalized floats handled in C#?

I have found something unexpected (to me) using the [Intel&#174; Architecture Code Analyzer](https://software.intel.com/en-us/articles/intel-architecture-code-analyzer) (IACA).

The following instruction using `[base+index]` addressing 

    addps xmm1, xmmword ptr [rsi+rax*1]

does not micro-fuse according to IACA. However, if I use `[base+offset]` like this

    addps xmm1, xmmword ptr [rsi]

IACA reports that it does fuse.

Section 2-11 of the [Intel optimization reference manual](http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html) gives the following as an example &quot;of micro-fused micro-ops that can be handled by all decoders&quot;

    FADD DOUBLE PTR [RDI + RSI*8]

and [Agner Fog&#39;s optimization assembly manual](http://www.agner.org/optimize/) also gives examples of micro-op fusion using `[base+index]` addressing. See, for example, Section 12.2 &quot;Same example on Core2&quot;. So what&#39;s the correct answer?

Micro fusion and addressing modes

I know that Numpy can use different backends like OpenBLAS or MKL. I have also read that MKL is heavily optimized for Intel, so usually people suggest to use OpenBLAS on AMD, right?

I use the following test code:
```python
import numpy as np

def testfunc(x):
    np.random.seed(x)
    X = np.random.randn(2000, 4000)
    np.linalg.eigh(X @ X.T)

%timeit testfunc(0)
```

I have tested this code using different CPUs:
- On **Intel Xeon E5-1650 v3**, this code performs in **0.7s** using **6 out of 12 cores**.
- On **AMD Ryzen 5 2600**, this code performs in **1.45s** using **all 12 cores**.
- On **AMD Ryzen Threadripper 3970X**, this code performs in **1.55s** using **all 64 cores**.

I am using the same Conda environment on all three systems. According to `np.show_config()`, the Intel system uses the MKL backend for Numpy (`libraries = [&#39;mkl_rt&#39;, &#39;pthread&#39;]`), whereas the AMD systems use OpenBLAS (`libraries = [&#39;openblas&#39;, &#39;openblas&#39;]`). The CPU core usage was determined by observing `top` in a Linux shell:

- For the **Intel Xeon E5-1650 v3** CPU (6 physical cores), it shows 12 cores (6 idling).
- For the **AMD Ryzen 5 2600** CPU (6 physical cores), it shows 12 cores (none idling).
- For the **AMD Ryzen Threadripper 3970X** CPU (32 physical cores), it shows 64 cores (none idling).

The above observations give rise to the following questions:

1. Is that normal, that linear algebra on up-to-date AMD CPUs using OpenBLAS is *that much slower* than on a six-year-old Intel Xeon? *(also addressed in Update 3)*
2. Judging by the observations of the CPU load, it looks like Numpy utilizes the multi-core environment in all three cases. How can it be that the Threadripper is even slower than the Ryzen 5, even though it has almost six times as many physical cores? *(also see Update 3)*
3. Is there anything that can be done to speed up the computations on the Threadripper? *(partially answered in Update 2)*

---

**Update 1:** The OpenBLAS version is 0.3.6. I read somewhere, that upgrading to a newer version might help, however, with OpenBLAS updated to 0.3.10, the performance for `testfunc` is still 1.55s on AMD Ryzen Threadripper 3970X.

---

**Update 2:** Using the MKL backend for Numpy in conjunction with the environment variable `MKL_DEBUG_CPU_TYPE=5` (as described [here][1]) reduces the run time for `testfunc` on AMD Ryzen Threadripper 3970X to only 0.52s, which is actually more or less satisfying. FTR, setting this variable via `~/.profile` did not work for me on Ubuntu 20.04. Also, setting the variable from within Jupyter did not work. So instead I put it into `~/.bashrc` which works now. Anyways, performing 35% faster than an old Intel Xeon, is this all we get, or can we get more out of it?

---

**Update 3:** I play around with the number of threads used by MKL/OpenBLAS:

[![run time by the number of threads and library][2]][2]

The run times are reported in seconds. The best result of each column is underlined. I used OpenBLAS 0.3.6 for this test. The conclusions from this test:
- **The single-core performance of the Threadripper using OpenBLAS is a bit better** than the single-core performance of the Xeon (11% faster), however, its single-core performance is even better when using MKL (34% faster).
- **The multi-core performance of the Threadripper using OpenBLAS is ridiculously worse** than the multi-core performance of the Xeon. What is going on here?
- **The Threadripper performs overall better than the Xeon**, when MKL is used (26% to 38% faster than Xeon). The overall best performance is achieved by the Threadripper using 16 threads and MKL (36% faster than Xeon).

---

**Update 4:** Just for clarification. No, I do not think that (a) [this][1] or (b) [that][3] answers this question. (a) suggests that *&quot;OpenBLAS does nearly as well as MKL&quot;*, which is a strong contradiction to the numbers I observed. According to my numbers, OpenBLAS performs ridiculously worse than MKL. The question is why. (a) and (b) both suggest using `MKL_DEBUG_CPU_TYPE=5` in conjunction with MKL to achieve maximum performance. This might be right, but it does neither explain *why* OpenBLAS is *that dead* slow. Neither it explains, why even with MKL and `MKL_DEBUG_CPU_TYPE=5` the **32-core Threadripper is only 36% faster than the six-year-old 6-core Xeon**.


  [1]: https://www.pugetsystems.com/labs/hpc/How-To-Use-MKL-with-AMD-Ryzen-and-Threadripper-CPU-s-Effectively-for-Python-Numpy-And-Other-Applications-1637/#TestsystemsAMDThreadripper3960x,Ryzen3900XandIntelXeon2175W
  [2]: https://i.stack.imgur.com/uVJV8.png
  [3]: https://stackoverflow.com/questions/63174453/when-you-have-an-amd-cpu-can-you-speed-up-code-that-uses-the-intel-mkl/63174454#63174454

Why is Numpy with Ryzen Threadripper so much slower than Xeon?

I am trying to profile and optimize algorithms and I would like to understand the specific impact of the caches on various processors.  For recent Intel x86 processors (e.g. Q9300), it is very hard to find detailed information about cache structure.  In particular, most web sites (including [Intel.com][1]) that post processor specs do not include any reference to L1 cache.  Is this because the L1 cache does not exist or is this information for some reason considered unimportant?  Are there any articles or discussions about the elimination of the L1 cache?

[edit]
After running various tests and diagnostic programs (mostly those discussed in the answers below), I have concluded that my Q9300 seems to have a 32K L1 data cache.  I still haven&#39;t found a clear explanation as to why this information is so difficult to come by.  My current working theory is that the details of L1 caching are now being treated as trade secrets by Intel.

  [1]: http://www.intel.com/products/processor/core2quad/specifications.htm

Where is the L1 memory cache of Intel x86 processors documented?

I want to check if Intel virtualization is enabled in my laptop or not (Lenovo Thinkpad, Win 10 64 bit). Is there any way available to check it without going to BIOS?

All Intel Solutions on Gang of Coders

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