All Cpu Architecture Solutions on Gang of Coders

Total of 47 Cpu Architecture Solutions

Why is processing a sorted array faster than processing an unsorted array?

JavaC++PerformanceCpu ArchitectureBranch Prediction

How do I achieve the theoretical maximum of 4 FLOPs per cycle?

C++AssemblyX86 64Cpu ArchitectureFlops

Deoptimizing a program for the pipeline in Intel Sandybridge-family CPUs

C++OptimizationX86IntelCpu Architecture

What is a retpoline and how does it work?

SecurityAssemblyX86Cpu ArchitectureSpectre

Difference between core and processor

CpuCoreCpu Architecture

What is the purpose of the "Prefer 32-bit" setting in Visual Studio and how does it actually work?

C#.NetVisual StudioCompilationCpu Architecture

What Every Programmer Should Know About Memory?

OptimizationMemoryX86Cpu ArchitectureCpu Cache

What is the difference between Trap and Interrupt?

X86Operating SystemKernelInterruptCpu Architecture

Why is a boolean 1 byte and not 1 bit of size?

C++BooleanByteCpu ArchitectureAbi

What is difference between sjlj vs dwarf vs seh?

C++Compiler ConstructionMingwCpu ArchitectureMingw W64

Why is processing an unsorted array the same speed as processing a sorted array with modern x86-64 clang?

C++PerformanceClangCpu ArchitectureBranch Prediction

Bubble sort slower with -O3 than -O2 with GCC

CGccX86 64Cpu ArchitectureCompiler Optimization

Write-back vs Write-Through caching?

CachingCpu ArchitectureCpu Cache

What is the "FS"/"GS" register intended for?

AssemblyX86Cpu ArchitectureCpu RegistersMemory Segmentation

Are there any smart cases of runtime code modification?

ExecutableCpu ArchitectureInstructionsSelf ModifyingPlatform Agnostic

Why do x86-64 systems have only a 48 bit virtual address space?

X86 64Virtual MemoryCpu Architecture

Why is x86 ugly? Why is it considered inferior when compared to others?

AssemblyX86MipsX86 64Cpu Architecture

What's the difference between a word and byte?

AssemblyByteCpu ArchitectureTerminologyWord

Why does Intel hide internal RISC core in their processors?

AssemblyX86IntelCpu Architecture

atomic operation cost

PerformanceAtomicCpu ArchitectureLock Free

Why is a conditional move not vulnerable to Branch Prediction Failure?

PerformanceAssemblyOptimizationCpu ArchitectureBranch Prediction

Detecting CPU architecture compile-time

C++CDetectionCpu ArchitectureCompile Time

Line size of L1 and L2 caches

CachingMemory ManagementCpu ArchitectureCpu Cache

What are stalled-cycles-frontend and stalled-cycles-backend in 'perf stat' result?

LinuxPerformanceOptimizationComputer ArchitectureCpu Architecture

How is CPU usage calculated?

AlgorithmPerformanceCpuCpu UsageCpu Architecture

Enhanced REP MOVSB for memcpy

PerformanceAssemblyX86Cpu ArchitectureMemcpy

Why is the loop instruction slow? Couldn't Intel have implemented it efficiently?

PerformanceAssemblyX86IntelCpu Architecture

What is a cache hit and a cache miss? Why would context-switching cause cache miss?

ConcurrencyLanguage AgnosticCpuCpu ArchitectureCpu Cache

how much memory can be accessed by a 32 bit machine?

32bit 64bitRamCpu Architecture

After update to Xcode 5 - ld: symbol(s) not found for architecture armv7 or armv7s linker error

CordovaStatic LibrariesCpu ArchitectureIos7Xcode5

Turing machine vs Von Neuman machine

Computer ScienceCpu ArchitectureTuring MachinesVon Neumann

How many CPU cycles are needed for each assembly instruction?

PerformanceAssemblyX86Cpu ArchitectureCpu Cycles

What is the difference between x64 and IA-64?

64 BitX86 64Cpu ArchitectureItanium

Determine target ISA extensions of binary file in Linux (library or executable)

LinuxShared LibrariesExecutableCpu ArchitectureInstruction Set

FLOPS per cycle for sandy-bridge and haswell SSE2/AVX/AVX2

CpuIntelCpu ArchitectureAvxFlops

Why is x86 little endian?

X86IntelEndiannessCpu ArchitectureMicroprocessors

Maximum memory which malloc can allocate

CMemory ManagementOperating SystemMallocCpu Architecture

Difference between x86, x32, and x64 architectures?

X8664 BitX86 64Cpu ArchitectureAbi

How are atomic operations implemented at a hardware level?

X86AtomicCpu ArchitectureLock FreeSmp

How do SMP cores, processes, and threads work together exactly?

MultithreadingOperating SystemMultiprocessingMulticoreCpu Architecture

How can I determine for which platform an executable is compiled?

C#PowershellCpu Architecture

Micro fusion and addressing modes

AssemblyX86IntelCpu ArchitectureIaca

What are some examples of non-Von Neumann architectures?

Cpu ArchitectureVon Neumann

How does an assembly instruction turn into voltage changes on the CPU?

AssemblyEmbeddedCpu Architecture

Where is the L1 memory cache of Intel x86 processors documented?

PerformanceIntelCpu ArchitectureCpu Cache

How does direct mapped cache work?

CachingSystemCpu Architecture

Is x86 RISC or CISC?

X86CpuCpu Architecture